For logic gates, if they want to negate, they use NOT gate or bubble immediately on basic gate(e.g NAND gate obtained by buble immediately on AND).

If the input is active low, they show it by 'bar' on head/top of the input.

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+5 votes

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Just dont go with bubbles. Its sometimes used to show an output/input.

For logic gates, if they want to negate, they use NOT gate or bubble immediately on basic gate(e.g NAND gate obtained by buble immediately on AND).

If the input is active low, they show it by 'bar' on head/top of the input.

For logic gates, if they want to negate, they use NOT gate or bubble immediately on basic gate(e.g NAND gate obtained by buble immediately on AND).

If the input is active low, they show it by 'bar' on head/top of the input.

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@sushant_gokhale, Can u explain this a bit ?

When the clock is at level 1, the output of NAND gate is 0 and hence, the output of 2nd FF toggles and goes to 0

clock is at 1

- Q
_{0}is 1 - Q
_{2}is 0

So NAND gate should be 1 right ? How it is 0 ? Im not getting this

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My final conclusion is mod -6 . @sushant preset will make ouput 1 but here active low is used so ff1 and ff3 are not always 1.

Count goes from 0-1-2-3-4 and then 5 comes and nand gate goes low positive edge making count to 7(111) instead of (101) and then on next negative edge, 000.

So count is 0-1-2-3-4-7. I think mod-6 will be the given answer.

Count goes from 0-1-2-3-4 and then 5 comes and nand gate goes low positive edge making count to 7(111) instead of (101) and then on next negative edge, 000.

So count is 0-1-2-3-4-7. I think mod-6 will be the given answer.

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@pc.

When its given **preset**, always start with all outputs set to 1.

When its given **clear, ** always start with all outputs set to 0.

Actually , I think I was wrong.

The output of 1st FF never changes and hence, there wont be a falling edge required for 2nd FF.

So, output is always 111.

It seems something wrong with question.

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I didn't know when preset is given we have to start with 1. Any refrence for that???

And even if I start with 111 I am getting same count.

And even if I start with 111 I am getting same count.

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@Rahul.

You are right. Bubble should normally indicate negation/ active low. But, they have **Pr** and not **Pr'**. So, this indicates that bubble simply needs to be ignored.

Now, preset is usually used withdown counters and hence, they count 111, 110, 101, ...

When clear is used, its usually up counter and hence, they count 000, 001, 010, ...

So, its not standard, but its good.

I predict somehing wrong with question.

See this:

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@Sushant / @Debashish I have understood that the given question is wrong as Preset will begin with 111. And It will always stay there. as Q0=Q2=1 and output through NAND gate is 0 and Preset is Active low.

In case instead of Preset Lets Assume it is Clear and Initial value 000 then what should be the ans?

Clock | Q0 | Q1 | Q2 | State |

0 | 0 | 0 | 0 | |

1 | 1 | 0 | 0 | 1 |

2 | 0 | 1 | 0 | 2 |

3 | 1 | 1 | 0 | 3 |

4 | 0 | 0 | 1 | 4 |

5 | 1 | 0 | 1 | 5 |

At clock t5 or lets say after 5 clock pulses Q0 and Q2 becomes 1 and through NAND gate they will become 0 and since preset is active low will set the contents to 000

Doubt - When will this happen? In clock t5 only? or in the next clock t6. And What is the significance of connecting clock with NAND gate?

If the output is cleared in t5 only then MOD will be 5 if it happens in t6 then MOD will be 6.

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@yash.

If thats the case, its mod-6 counter. The output of all FF's will be cleared when its level 1 of the 6th clock pulse.

If thats the case, its mod-6 counter. The output of all FF's will be cleared when its level 1 of the 6th clock pulse.

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and since preset is active low will set the contents to 000

@yashgupta1992 .... only Q1 cleared or all ?

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@Debashish.

Its basically asynchronous up counter. But you dont know upto what it will count i.e. if 0 is the lower end and last count is 'n' then you dont know what is 'n'. So, you need to start counting from somewhere.

Then why not start counting from 0? If you know any intermediate state, then also its fine. But, you know tht as there is clear input, 0 is definitely one of the states. Hnce, start with 0.

Its basically asynchronous up counter. But you dont know upto what it will count i.e. if 0 is the lower end and last count is 'n' then you dont know what is 'n'. So, you need to start counting from somewhere.

Then why not start counting from 0? If you know any intermediate state, then also its fine. But, you know tht as there is clear input, 0 is definitely one of the states. Hnce, start with 0.

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@Debashish all of them. Sorry, I meant that since Q0 and Q1 are anyways applied 1 directly. Thus when its t5 the outcome of NAND gate is 0 which will Clear all the flip flops.

@Sushant, that is where I am having problem in understanding. . Once the outcome is 0 of NAND gate in t5 why wait for next clock? Usually we clear them in same clock isnt it?

Here are some similar models -

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@sushant, I asked something else.

I am asking ::

- At 5th clock falling edge , state is <1,0,1>
- After that If we are considering it as clear : then which one of three FF are cleared ?
- you are saying all ?

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@Debashish. Thats the flaw with the diagram. Again if you clear only the middle FF, then it will be mod-1 counter ,right? So, just assume for problem solving that all are cleared :P Dont kill me

@Yash. After the falling edge of clock, the FF's enter 101 state. On level 1 of 5th clock pulse, FF's are still in state 100 and hence, NAND gate output is 1.

@Yash. After the falling edge of clock, the FF's enter 101 state. On level 1 of 5th clock pulse, FF's are still in state 100 and hence, NAND gate output is 1.

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Ahh, @Debashish I got your point. Sorry in my case I am assuming the other two will be applied 0 directly instead of 1 making them clear at t5 along with Q1

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in the morning I have posted one image...regarding this, after 5th falling edge if we wait for $\text{cycle-time/2}$ , for the next half **high** clock signal then NAND clears Q1. But Q1 is already $0$ in the last falling edge. SO no change, So can the overall state go to $<1,1,0>$ in the upcoming 6th falling edge ?

+3 votes

Best answer

Importance of Preset and Clear Inputs in Flip-Flops and Usage

https://www.youtube.com/watch?v=mXoQ4WAQ0qk

Importance Points to be noticed when doing Aysnchronous Flip Flop Constructions

https://www.youtube.com/watch?v=fKVZpupyP_o&index=186&list=PLBlnK6fEyqRjMH3mWf6kwqiTbT798eAOm

Given Flip Flop

- Negative Edge Triggered . Output will change in falling edge

No matter what the values of J and K is

- Whenever $\text{CLEAR} =0$ then Output $\text{Q} =0$ [Reset]
- Whenever $\text{PRESET} =0$ then Output $\text{Q} =1$ [Set]

Hence the output sequence is $0-1-2-3-4-7-6-7-0$

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@pc. Your correct. Just tell us what did you assume: preset/clear for which FF's?

I also doubt:

Whenever PRESET=0 then Output Q=1 [Set]

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Did u watch those videos ? It cosumes nealry 10mins each But will get a great picture compared to when I explain the stuff :D :P

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@pc. I saw the first video? But, then what's "preset bar" or preset prime in picture I have pasted or its just variable notation(which doesnt matter)?

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Hey all.....got the best link.

http://www.allaboutcircuits.com/textbook/digital/chpt-10/asynchronous-flip-flop-inputs/

So, @pc you are correct.

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Whenever $\text{PRESET is } 0 \Leftrightarrow \overline{\text{PRESET}}\text{ is }= \overline{0}=1$

[when ACTIVE LOW ]

[when ACTIVE LOW ]

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@Sushant_Gokhale , in your link one is ACTIVE LOW . other is ACTIVE HIGH so $\text{PRESET}$ and $ \overline{\text{PRESET}}$ looks like same

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