5 votes 5 votes Identify the mod value of the given riple counter 5 6 7 8 Digital Logic made-easy-test-series cbt-2017 digital-logic ripple-counter-operation + – pC asked Jan 22, 2017 edited Mar 5, 2019 by adeebafatima1 pC 2.7k views answer comment Share Follow See all 42 Comments See all 42 42 Comments reply Rahul Jain25 commented Jan 22, 2017 reply Follow Share Is it mod-7 . I am getting count sequence of (0-1-0-3-2-1-5) 0 votes 0 votes Anup patel commented Jan 23, 2017 reply Follow Share It should be mod 5 i.e 0,1,2,3,4,5 when 101 will arrive there will be unstable state but ans is given as mod 6.... 0 votes 0 votes dd commented Jan 23, 2017 reply Follow Share pC//I am getting ..0,1,2,3,4,5,6,7,1,2,3,4,5,6,7,1,2,3,4,5,6,7,1.... counting 7 pulses only after intial phase, so mod 7.. I may be wrong ...please tell what you got. 0 votes 0 votes Anup patel commented Jan 23, 2017 reply Follow Share @ Debashish Deka when 5 i.e 101 will appear counter become unstable i.e pr0,pr1 and pr2 will be active low .so it would be 000,001,010,011,100,101(a doubt whether it will count 101 or not). So, MOd 5 or mod 6 should be answer. 0 votes 0 votes bad_engineer commented Jan 23, 2017 i reshown by bad_engineer Jan 23, 2017 reply Follow Share Yup I also marked as 5 I don't understand why they took 6 also 0 votes 0 votes Rahul Jain25 commented Jan 23, 2017 reply Follow Share Second and third FF's should change transition only when first FF goes from 1-0, isn't it??? Then how is count like 1-2-3-4.. Possible.@ PC also give the count sequence along with mod value. 0 votes 0 votes Anup patel commented Jan 23, 2017 reply Follow Share second will be affeccted by first only (i.e when first move from 1 to 0 )and third wil be affected by second(i.e when second move from 1 to 0) 0 votes 0 votes dd commented Jan 23, 2017 reply Follow Share My argument may be completely invalid, but here is what I thought . 1 votes 1 votes dd commented Jan 23, 2017 reply Follow Share if above diagram is wrong..then please someone show correct changes after pulse 5 ? 0 votes 0 votes pC commented Jan 23, 2017 reply Follow Share @Debashish_Deka , I have no answers since I have got few things to get clarified What is importance of -ve edge here ? ie When do the FF will be active What is the input to NAND gate ( initially) ? When do the first Flip-Flop will be ACTIVE 0 votes 0 votes Rahul Jain25 commented Jan 23, 2017 reply Follow Share When output of ff1 goes from 1-0 now FF-2 can change output, When ff2 goes from 1-0 then only ff-3 can change output. 0 votes 0 votes Rahul Jain25 commented Jan 23, 2017 reply Follow Share For my count sequence NAND nand is not doing anything significant. Anyway what is given count sequence and mod -value??? 0 votes 0 votes dd commented Jan 23, 2017 reply Follow Share $FF$ are $-ve$ edge triggered. $Q0$ will change state on every time when clock goes from $1$ to $0$ $Q1$ will change state on every time when $Q0$ goes from $1$ to $0$ $Q2$ will change state on every time when $Q1$ goes from $1$ to $0$ 0 votes 0 votes dd commented Jan 23, 2017 reply Follow Share Frankly speaking I am not confident enough in digital ...if anyone sure enough with a good diagram please feel free to post. 0 votes 0 votes dd commented Jan 23, 2017 reply Follow Share @bad_engineer + @Anup patel ..I hope you have some logic regarding mod 6 or 5 ... please help in this case. 0 votes 0 votes Sushant Gokhale commented Jan 23, 2017 reply Follow Share @Debashish. I think the following. The preset is always 1 for JK0 and JK2 and hnce, Q0 and Q2 will always be 1. Now, we observe that when clock is at level 0, the output of NAND gate is 1 and hence, the output of 2nd FF is also 1. When the clock is at level 1, the output of NAND gate is 0 and hence, the output of 2nd FF toggles and goes to 0 So, states are: 111, 101, 111, 101 ................only 2 states So, mod-2 counter. 0 votes 0 votes dd commented Jan 23, 2017 reply Follow Share yes..sorry for the above comemnt ! 0 votes 0 votes dd commented Jan 23, 2017 reply Follow Share preset 1 does not mean o/p will be always high 0 votes 0 votes Sushant Gokhale commented Jan 23, 2017 reply Follow Share Preset means it sets the output to high. At all other times, its kept to 0. 0 votes 0 votes Sushant Gokhale commented Jan 23, 2017 reply Follow Share @vasu. If its active low, they show a 'bar' on head of preset. Here, preset is active high. 0 votes 0 votes Rahul Jain25 commented Jan 23, 2017 reply Follow Share @sushant I think you are right it should be mod 2.. 1 votes 1 votes Vasu_gate2017 commented Jan 23, 2017 reply Follow Share @sushant but then had bubbled Pr.........so will not it make Pr from 1 to 0 ....... 0 votes 0 votes Sushant Gokhale commented Jan 23, 2017 reply Follow Share Just dont go with bubbles. Its sometimes used to show an output/input. For logic gates, if they want to negate, they use NOT gate or bubble immediately on basic gate(e.g NAND gate obtained by buble immediately on AND). If the input is active low, they show it by 'bar' on head/top of the input. 0 votes 0 votes pC commented Jan 23, 2017 reply Follow Share @sushant_gokhale, Can u explain this a bit ? When the clock is at level 1, the output of NAND gate is 0 and hence, the output of 2nd FF toggles and goes to 0 clock is at 1 Q0 is 1 Q2 is 0 So NAND gate should be 1 right ? How it is 0 ? Im not getting this 0 votes 0 votes Rahul Jain25 commented Jan 23, 2017 reply Follow Share My final conclusion is mod -6 . @sushant preset will make ouput 1 but here active low is used so ff1 and ff3 are not always 1. Count goes from 0-1-2-3-4 and then 5 comes and nand gate goes low positive edge making count to 7(111) instead of (101) and then on next negative edge, 000. So count is 0-1-2-3-4-7. I think mod-6 will be the given answer. 0 votes 0 votes Sushant Gokhale commented Jan 23, 2017 reply Follow Share @pc. When its given preset, always start with all outputs set to 1. When its given clear, always start with all outputs set to 0. Actually , I think I was wrong. The output of 1st FF never changes and hence, there wont be a falling edge required for 2nd FF. So, output is always 111. It seems something wrong with question. 0 votes 0 votes Sushant Gokhale commented Jan 23, 2017 reply Follow Share @Rahul. Thats not active low. I bet on this.....200% 0 votes 0 votes Rahul Jain25 commented Jan 23, 2017 reply Follow Share Bubble means active low right. 0 votes 0 votes Rahul Jain25 commented Jan 23, 2017 reply Follow Share I didn't know when preset is given we have to start with 1. Any refrence for that??? And even if I start with 111 I am getting same count. 0 votes 0 votes Sushant Gokhale commented Jan 23, 2017 i edited by Sushant Gokhale Jan 24, 2017 reply Follow Share @Rahul. You are right. Bubble should normally indicate negation/ active low. But, they have Pr and not Pr'. So, this indicates that bubble simply needs to be ignored. Now, preset is usually used withdown counters and hence, they count 111, 110, 101, ... When clear is used, its usually up counter and hence, they count 000, 001, 010, ... So, its not standard, but its good. I predict somehing wrong with question. See this: 0 votes 0 votes yg92 commented Jan 23, 2017 reply Follow Share @Sushant / @Debashish I have understood that the given question is wrong as Preset will begin with 111. And It will always stay there. as Q0=Q2=1 and output through NAND gate is 0 and Preset is Active low. In case instead of Preset Lets Assume it is Clear and Initial value 000 then what should be the ans? Clock Q0 Q1 Q2 State 0 0 0 0 1 1 0 0 1 2 0 1 0 2 3 1 1 0 3 4 0 0 1 4 5 1 0 1 5 At clock t5 or lets say after 5 clock pulses Q0 and Q2 becomes 1 and through NAND gate they will become 0 and since preset is active low will set the contents to 000 Doubt - When will this happen? In clock t5 only? or in the next clock t6. And What is the significance of connecting clock with NAND gate? If the output is cleared in t5 only then MOD will be 5 if it happens in t6 then MOD will be 6. 0 votes 0 votes Sushant Gokhale commented Jan 23, 2017 reply Follow Share @yash. If thats the case, its mod-6 counter. The output of all FF's will be cleared when its level 1 of the 6th clock pulse. 0 votes 0 votes dd commented Jan 23, 2017 reply Follow Share and since preset is active low will set the contents to 000 @yashgupta1992 .... only Q1 cleared or all ? 0 votes 0 votes Sushant Gokhale commented Jan 23, 2017 reply Follow Share @Debashish. All cleared 0 votes 0 votes dd commented Jan 23, 2017 reply Follow Share why all cleared please explain in short 0 votes 0 votes Sushant Gokhale commented Jan 23, 2017 reply Follow Share @Debashish. Its basically asynchronous up counter. But you dont know upto what it will count i.e. if 0 is the lower end and last count is 'n' then you dont know what is 'n'. So, you need to start counting from somewhere. Then why not start counting from 0? If you know any intermediate state, then also its fine. But, you know tht as there is clear input, 0 is definitely one of the states. Hnce, start with 0. 0 votes 0 votes yg92 commented Jan 23, 2017 reply Follow Share @Debashish all of them. Sorry, I meant that since Q0 and Q1 are anyways applied 1 directly. Thus when its t5 the outcome of NAND gate is 0 which will Clear all the flip flops. @Sushant, that is where I am having problem in understanding. . Once the outcome is 0 of NAND gate in t5 why wait for next clock? Usually we clear them in same clock isnt it? Here are some similar models - https://gateoverflow.in/37650/finding-modulus-of-a-counter https://gateoverflow.in/1234/gate2007-36 0 votes 0 votes dd commented Jan 23, 2017 reply Follow Share @sushant, I asked something else. I am asking :: At 5th clock falling edge , state is <1,0,1> After that If we are considering it as clear : then which one of three FF are cleared ? you are saying all ? 0 votes 0 votes dd commented Jan 23, 2017 reply Follow Share NAND o/p is connected to Q1 only right ? 0 votes 0 votes Sushant Gokhale commented Jan 23, 2017 reply Follow Share @Debashish. Thats the flaw with the diagram. Again if you clear only the middle FF, then it will be mod-1 counter ,right? So, just assume for problem solving that all are cleared :P Dont kill me @Yash. After the falling edge of clock, the FF's enter 101 state. On level 1 of 5th clock pulse, FF's are still in state 100 and hence, NAND gate output is 1. 0 votes 0 votes yg92 commented Jan 23, 2017 reply Follow Share Ahh, @Debashish I got your point. Sorry in my case I am assuming the other two will be applied 0 directly instead of 1 making them clear at t5 along with Q1 0 votes 0 votes dd commented Jan 23, 2017 reply Follow Share in the morning I have posted one image...regarding this, after 5th falling edge if we wait for $\text{cycle-time/2}$ , for the next half high clock signal then NAND clears Q1. But Q1 is already $0$ in the last falling edge. SO no change, So can the overall state go to $<1,1,0>$ in the upcoming 6th falling edge ? 0 votes 0 votes Please log in or register to add a comment.
Best answer 3 votes 3 votes Importance of Preset and Clear Inputs in Flip-Flops and Usage https://www.youtube.com/watch?v=mXoQ4WAQ0qk Importance Points to be noticed when doing Aysnchronous Flip Flop Constructions https://www.youtube.com/watch?v=fKVZpupyP_o&index=186&list=PLBlnK6fEyqRjMH3mWf6kwqiTbT798eAOm Given Flip Flop Negative Edge Triggered . Output will change in falling edge No matter what the values of J and K is Whenever $\text{CLEAR} =0$ then Output $\text{Q} =0$ [Reset] Whenever $\text{PRESET} =0$ then Output $\text{Q} =1$ [Set] Hence the output sequence is $0-1-2-3-4-7-6-7-0$ pC answered Jan 23, 2017 selected Jan 23, 2017 by Sushant Gokhale pC comment Share Follow See all 15 Comments See all 15 15 Comments reply Show 12 previous comments Sushant Gokhale commented Jan 23, 2017 reply Follow Share bubble and (preset or preset bar) -> Qn = 1 When bubble, input should be 0. 0 votes 0 votes Sushant Gokhale commented Jan 24, 2017 reply Follow Share @pc. I think it should be mod 7 counter. I started from 111. So, the outputs for Q0 - Q1 - Q2 will be: 111 000 100 010 110 001 001 Now, 001 is stable for 1/2 cycle of clock. But, this output is stable. So, its mod-7 counter. 0 votes 0 votes vaishali jhalani commented Jan 24, 2017 reply Follow Share Yes..I am also getting mod 8. But in solution it is given that at 6th clock output is 111, I am not getting this. 0 votes 0 votes Please log in or register to add a comment.