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edited | 542 views
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R0 <- R1+R2

R4 <- R0

R5 <- R4+R0

R6 <- R5+R4

Hence Total Cycle = $9$

Without Operand Forwarding = $14$ cycles

Hence, Total cycles saved = $14 - 9 = 5$ cycles.

by Junior (637 points)
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Question is asked the number of cycles that is saved !
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answer should be 8 as w/o operand forwarding we have to wait till  WB stage for executing next instn as instructions are dependent. w/o O.F it will take 17 clk cycles whereas it is taking 9 clk cycle with O.F.

so answer should be 17-9 = 8
+1

Cycles saved = 4

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for Instruction 3 why need to wait till WB stage Question says Load output is available on 4th stage
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Which diag are you talking about?

diag 1: WB of 3rd ins. executes in 1st half cycle and ID of 4th ins. in 2nd half.

diag 2: MM takes 1 complete cycle. So, ID of next instruction has to go to next cycle.
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you cant execute ID  of I2 with WB  of I1 as there is no data forwarding involved in case 1. yeah data is available after MM for load operation but it can't be forwarded, as no data forwarding involved. we need to wait till WB stage of I1. correct me if i am wrong.
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I was talking about with 2nd diagram

if the Question says Load output is available after 4th stage then we can take in the next cycle but it says it is present in the 4th cycle   i have doubt here..
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Guys, I seriously suggest solve these examples. They are selective. They will cover everything.

https://gateoverflow.in/8218/gate2015-2_44
- RD stage of next instruction can overlap with EX of previous due to split-phase technique

https://gateoverflow.in/34735/pipelining-without-operand-forwarding

https://gateoverflow.in/1391/gate2005-68#a77905
-RD stage of next instruction can overlap with WB stage of previous indtruction due to split phase technique.

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Also, solve the gate questions that have been posted as coments in these questions. Give as much time as possible till you completely understand them.
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Yup I got my mistake now....
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@pikachu.

ID of next instruction overlaps with WB of previous because WB can execute in 1st half cycle and ID in next half.

Thats why I gave links. SOlve those. You will never forget pipelining :P
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@sushant,one correction ..in your second diagram,,with operand forwarding.you dun need to give stall at clock cycle 4 for ID stage of third instruction .we can execute EX stage of R4 <- R0 and ID stage of R5 <- R4+R0 together as in operand forwarding ,this wont create any issue

as in this question.,https://gateoverflow.in/1391/gate2005-68#a77905

@pC has said that data forwardiing takes care of this.hence you can do these two stages together,hence total cycles for operna forwarding will be 9

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@Akriti.

So, unless, R4 is loaded which is done at end of 4th stage, we cant go for ID of 3rd instruction.
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@sushant,see in that link again.in that also dirst instrution is a LOAD instruction whihc is loading value to L0 and third instruction is ADD which need L0,still we have done EX and ID together..pls check that once again.see pC answer
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ok, will check
+1
@Akriti. You are right. I did forwarding to ID stage by mistake. Instead, i woud have done that directly to EX stage.

My Approach:

Default in previous years Gate it has been observed that without pipelining we assume the split phase scenerio. The WB stage will write the output during rising edge of clock and ID stage will fetch at the falling edge of clock. Hence, WB and ID stage can overlap in “without-pipelining”. The number of clock cycles will be

14 – without pipelining

9   - with pipelining ( Which is correct in Skraj's solution )

Hence Ans – 14-9 = 5

Without Pipelining :

 1 2 3 4 5 6 7 8 9 10 11 12 13 14 I1 F D X M W I2 F D X M W I3 F D X M W I4 F D X M W
by Active (3.2k points)
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The WB stage will write the output during rising edge of clock and ID stage will fetch at the falling edge of clock. is it always true.??

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@Ravi No, But usually from previous year gate questions that is what they usually go with..