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2 Answers

Best answer
5 votes
5 votes

R0 <- R1+R2

R4 <- R0

R5 <- R4+R0

R6 <- R5+R4

Hence Total Cycle = $9$


Without Operand Forwarding = $14$ cycles

Hence, Total cycles saved = $14 - 9 = 5$ cycles.

selected by
2 votes
2 votes

My Approach:

Default in previous years Gate it has been observed that without pipelining we assume the split phase scenerio. The WB stage will write the output during rising edge of clock and ID stage will fetch at the falling edge of clock. Hence, WB and ID stage can overlap in “without-pipelining”. The number of clock cycles will be

14 – without pipelining

9   - with pipelining ( Which is correct in Skraj's solution )

Hence Ans – 14-9 = 5

Without Pipelining : 

1

2

3

4

5

6

7

8

9

10

11

12

13

14

I1

F

D

X

M

W

I2

F

D

X

M

W

I3

F

D

X

M

W

I4

F

D

X

M

W

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