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Suppose that in 250 memory references there are 30 misses in first level cache and 10 misses in second level cache. Assume that miss penalty from the L2 cache memory are 50 cycles. The hit time of L2 cache is 10 cycles. The hit time of the L1 cache is 5 cycles. If there are 1.25 memory references per instruction, then the average stall cycles per instruction is ________.

in CO and Architecture by Active (2.7k points)
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  • Miss penalty of L1 = hit time of L2 + (miss rate of L2 * miss penalty of L2), (Therefore, we can see that miss penalty of L1 already includes miss penalty of L2)
  • Therefore, miss penalty of L1 = 10 c + ((10/30) * 50) c = (80/3) c
  • No. of stalls per memory reference = miss rate of L1 * miss penalty of L1 ,(Stalls are introduced due to misses in L1 cache)
  • Therefore, No. of stalls per memory reference = (30/250) * (80/3) = (16/5) stalls
  • Since each instruction makes 1.25 mem references (given), therefore, No. of stalls per instruction = (16/5) * 1.25 = 4 stalls
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