The basic process starts with converting the virtual address to a physical address; if possible, this relies on the TLB cache’s stored entry that maps virtual address to physical address, but if this fails, then the page table must be consulted in physical or virtual memory. Once the physical address is available, the processor can attempt to retrieve the actual value from the data cache, but if this fails, then the value must be read from physical memory.
Option A
It is not true,
Reason : a TLB miss can occur without a subsequent page fault. The TLB is typically much smaller than physical memory. It is quite possible that a page’s virtual-to physical mapping will get forced out of the TLB without getting forced out of physical memory. So miss in TLB does not mean a page fault always.
Option B :
it is also not true,
Reason : a data cache miss can occur without a subsequent page fault. Like the TLB, the data cache is much smaller than the physical memory. It is quite possible that page content will get forced out of the cache without getting forced out of physical memory.
Option C :
It is true,
Reason : since virtual-to-physical address translation relies on checking the TLB cache rather than the data cache. Hence, the translation cannot generate a data cache fault. Although the ensuing load from the physical address can still generate a data cache miss, this still only have in total one data cache miss.
Option D :
It is False .
Reason : Because retrieving data from disk takes milliseconds ( long enough with repect to CPU ) , whereas retrieving data from cache takes microseconds, computers will never generate page faults until after unsuccessfully testing the cache. Hence, if a page fault occurs, then a cache miss must have been performed before that fault.
Hence it is clear from these options that correct choice is C .
