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7 votes
7 votes
There are 25 minterms in the SOP.  Number of NAND gates = Number of minterms + 1 = 25+1=26.
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5 votes
5 votes
AB+BC+AC=((AB)'(BC)'(AC)')'

(A+B)(A+C)(B+C)=((A+B)'+(A+C)'+(B+C)')'

 

Number of NAND gates = Number of minterms + 1 = 25+1=26.
2 votes
2 votes
AND-OR realization is equal to NAND-NAND realization. So total AND and OR is (25 + 1) = 26 NAND gate needed.
1 votes
1 votes
  • (SOP) AND-OR realisation $\equiv$ NAND-NAND realisation
     
  • (POS) OR-AND realisation $\equiv$ NOR-NOR realisation

See this: https://www.electrical4u.com/electrical-mcq.php?subject=digital-electronics&page=18

http://www.ece.ualberta.ca/~lkurgan/EE280/SN-15.pdf


AB, BC, CD...YZ require $25$ 2-input AND gates.

Then, we can OR all of them with a $single$ 25-input OR gate.

 

This is equivalent to using NAND gates of the exact same pattern. We will need $25$ 2-input NAND gates, and $1$ 25-input NAND gate.

So, 26 NAND gates.


See the image provided in Akash Dinkar's comment for clarity.

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