Question

Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associative cache. Assume that the cache has a line size of four 32-bit words. Draw a block diagram of this cache showing its organization and how the different address fields are used to determine a cache hit/miss. Where in the cache is the word from memory location ABCDE8F8 mapped?

Comments

how is word offset = 7 bits?? its not bit addressable???

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line size of four 32-bit words. = 4*32 = 128 = 2⁷ isnt?

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Is it bit addressable? How u concluded that it is bit addressable?

Answer 1

16 Kb cache size.

4 way set associative.

Line size = 4*32 bit = 16 bytes.

Here, in question "word" is mentioned and even

"Where in the cache is the word from memory location"

is asked. So, word addressing is in use. So, offset bits = 2 for 4 words.

#sets=no of lines/p(way)

#lines=cache size /line size = $2^{10}$

#sets = $\frac{2^{10}}{4} = 256$

tag(22 bit)

sets( 8 bit)

block size(2 bit)

 now addrees is ABCDE8F8

its binary from is :1010 1011 1100 1101 1110 1000 1111 1000

<1010 1011 1100 1101 1110 10> <00 1111 10> <00>

it is mapped to set number 62 in cache.

Comments

yes..

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@Arjun sir....I think it should be 62 not 63....

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Arjun Sir, i Did not understood how block offset is 2 bits. How is that possible please clear my doubt ?? Why 2 bits for 4 words ?