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I have gone through these types of questions but I'm unable to understand. how to appraoch these questions? And during the dma transfer, cpu is considered to be idle. before and after that it can do its own work. Where am I wrong?

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Regarding DMA burst mode ,where data to be transferred is k bytes, speed of i/o device is x and speed of bus is y.

1.) I/O device prepares k bytes of data in its buffer for k/x secs meanwhile CPU is operational.Then it request CPU for bus access where some time is spent in initialisaation and then takes k/y secs to transfer the data to memory.

If the speed of the bus is  mentioned . We use this approach.

2.) DMA controller requests for bus access, CPU takes some time for initilazing DMA then device transfers k bytes directly to the memory in k/x sec

If the speed of the bus is not mentioned . We use this approach.

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You can try this approach also...

As we know (DMA have preparation time and transfer time) and in question, it is given that DMA is taking a cycle of 50 μsec (which is nothing but transfer time )

now, for preparation time you have to get transfer time of data in that disk whose surfaces and tracks are given

rotation time is given as 3600rpm

for single rotation --> 60/3600

                           --> 16msec

and in single revolution disk can transfer a track data which is 256 sectors each having 512B

i.e. 128KB

16msec -->128KB

1sec    --> 8MB

Hence we can conclude that device having the speed of 8MBps now for writing it is reading 5B word so preparation time for 5B will be

8MB  -->  1sec

5B  -->  0.625μsec(preparation time)

%CPU blocked due to DMA = Transfer time / (transfer time + preparation time)

                                             = 50 / 50.625

                                             =  98.76

Hence answer will be 98.76% of the time CPU gets blocked

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