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Three 4 bit shift registers are connected in cascade as shown in figure below. Each register is applied with

A 4 bit data 1011 is applied to the shift register 1. What is the minimum number of clock pulses required to get same input data at output are with same clock?

edited | 1.3k views
+2
Clock SISO SIPO PISO Output
0 0000 0000 0000
1 1000 0000 0000
2 1100 0000 0000
3 0110 0000 0000
4 1011 0000 0000
5 0101 1000 0000
6 0010 1100 1000
7 0001 0110 1100 0
8 0000 1011 0110 0
9 0000 0101 1011 1
10 0000 0010 0101 11
11 0000 0001 0010 011
12 0000 0000 0001 1011

I think this should be ans...

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After the 4th edge last FF of the first register will get OUTPUT value, but it will not be loaded to the second register.

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This is correct of course
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@Lokesh . add it as answer. nice tabular format

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@Lokesh . Isn't it true that SISO takes n i/p clk pulse and n-1 o/p clk pulse? Then how here we are taking total 8 clk cycles instead of just 7(4i/p +3o/p) ?

Clock SISO SIPO PISO Output
0 0000 0000 0000
1 1000 0000 0000
2 1100 0000 0000
3 0110 0000 0000
4 1011 0000 0000
5 0101 1000 0000
6 0010 1100 1000
7 0001 0110 1100 0
8 0000 1011 0110 0
9 0000 0101 1011 1
10 0000 0010 0101 11
11 0000 0001 0010 011
12 0000 0000 0001 1011

12 Clock Pulses is correct answer

by Boss (11.6k points)
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how can the output of 9th cycle be 1 since the s3 gets 1011 in 9 th cycle it cant produce output in same cycle
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1011 is not the input to S3 in 9th cycle ...its actually his output..but as it is serial out ...so only last bit can be forwarded
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@lokesh,how  in 6th clock cyles,PISO got 1 in its first flip flop.i am cnfused
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@lokesh in 8th cycly the msb of s3 had 0 now in piso every at every cycle the output is the msb of last cycle hence at 9th cycle the output still should be 0

from 10th cycle the output sequence should start
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@Akriti sood

output of SIPO in 5th cycle is input to the PISO in 6th cycle
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@Pankaj Joshi

Shift registers can shift the bits in left or right direction depends on its implementation

so there is not any restriction that MSB will be output always

here LSB is output as it is shifting left-ro-right
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@lokesh..how is it so??i am not able to understand the reason..can you pls explain
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in SIPO,output is parallely catched from all flip flops.while in PISO,input is parallely catched..so,,how is it happening??
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@lokesh

regarding msb its my fault I was taking considering msb towards the right hand side I should have explained my convention

but going by your convention

in 8th cycle lsb is still 0

so output can''t be 1 in 9th cycle
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lsb of 9th cycle is output not 8th cycle
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@Akriti
all 3 registers are connected in a synchronous manner
so all registers are active at a time...so when SIPO generates output...that output will be available for PISO in the same cycle....but to take it as input PISO will require next cycle...internal structure is nothing but flip-flops