Three 4 bit shift registers are connected in cascade as shown in figure below. Each register is applied with
A 4 bit data 1011 is applied to the shift register 1. What is the minimum number of clock pulses required to get same input data at output are with same clock?
I think this should be ans...
After the 4th edge last FF of the first register will get OUTPUT value, but it will not be loaded to the second register.
@Lokesh . add it as answer. nice tabular format
12 Clock Pulses is correct answer