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Three 4 bit shift registers are connected in cascade as shown in figure below. Each register is applied with

A 4 bit data 1011 is applied to the shift register 1. What is the minimum number of clock pulses required to get same input data at output are with same clock?

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Clock SISO SIPO PISO Output
0 0000 0000 0000  
1 1000 0000 0000  
2 1100 0000 0000  
3 0110 0000 0000  
4 1011 0000 0000  
5 0101 1000 0000  
6 0010 1100 1000  
7 0001 0110 1100 0
8 0000 1011 0110 0
9 0000 0101 1011 1
10 0000 0010 0101 11
11 0000 0001 0010 011
12 0000 0000 0001 1011

12 Clock Pulses is correct answer

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