Pipeline (With split phase- With forwarding)

Question

A $5-$ stage pipelined processor has IF,ID,EX,MEM and WB . WB stage operation is divided into two parts. In the first part register write operation and in second part register read operation is performed. The latency of those stages are $300,400,500,500,300$ (in nano seconds) respectively.Consider the following code executed on this processor, operand forwarding is used in the pipeline

Instruction No.	Instruction	Meaning of Instruction
$I_{1}$	ADD $R_{3},R_{2},R_{4}$	$R_{3} <- R_{2} + R_{4}$
$I_{2}$	SUB $R_{6},R_{4},R_{3}$	$R_{6} <- R_{4} - R_{3}$
$I_{3}$	ADD $R_{7},R_{5},R_{3}$	$R_{7} <- R_{5} + R_{3}$
$I_{4}$	SUB $R_{1},R_{7},R_{4}$	$R_{1} <- R_{7} - R_{4}$

The program execution time__________ns?

Comments

@pc explain pls

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iS IT 4000 ns? Since the latency of each stage will be the largest one i.e 500 and it requires 8 clock cycles to execute all instructions.

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yes using operand forwarding 4000 ns  also . given in question split acces WB/ID.

Answer 1

R3 <-- R2 + R4

R6 <-- R4 - R3

R7 <-- R5 + R3

R1 <-- R7 - R4

I/C	1	2	3	4	5	6	7	8
I1	IF	ID	EX	MEM	WB
I2		IF	ID	EX	MEM	WB
I3			IF	ID	EX	MEM	WB
I4				IF	ID	EX	MEM	WB

This Instruction Pipeline takes 8 Instruction Cycle. And each Stage takes different latency .

Maximum Latency of stage is 500.

Hence Total Program execution time is = (Maximum latency) * (Total Cycle)

                                                         = 500 * 8

                                                         = 4000

Answer 2

$R_{3} <- R_{2} + R_{4}$

$R_{6} <- R_{4} - R_{3}$

$R_{7} <- R_{5} + R_{3}$

$R_{1} <- R_{7} - R_{4}$

Here, $1st$ and $2nd$ instruction has RAW dependency, similarly $3rd$ and $4th$ instruction has RAW dependency.

• Given, in WB stage first part register write operation is performed and $2nd$ part read operation performed.
• Maximum latency among stages is $500ns.$

Now, according to our assumption WB stage works for write and ID stage is for read an instruction. So, this can be done in one stage.

I/C

1

2

3

4

5

6

7

8

9

10

11

12

$I_{1}$

IF

ID

EX

MEM

WB

$I_{2}$

IF

ID

EX

MEM

WB

$I_{3}$

IF

ID

EX

MEM

WB

$I_{4}$

IF

ID

EX

MEM

WB

 

So, according to question , program execution time will be $8\times 500=4000ns$

 

Comments

Operand forwarding is mentioned in question, please check.

How to use it?  - should be listen NPTEL or read standard book

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@Shaik Masthan

yes, forwarding possible to EX-EX stage, as it is not LOAD instruction, right? It is an ADD or SUB operation, which can forward EX-EX stage 

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Forwarding can remove stalls.

So, in this question, this following line not causing any effect,right?

in WB stage first part register write operation is performed and 2nd part read operation performed.