0 votes 0 votes Correct Resilt Vasu_gate2017 asked Jan 29, 2017 Vasu_gate2017 500 views answer comment Share Follow See 1 comment See all 1 1 comment reply ankush007 commented Jan 28, 2019 reply Follow Share Tclk >= 2 * 2 ns + 1 ns Tclk >= 5 ns or 200MHZ option B is right :) 0 votes 0 votes Please log in or register to add a comment.
0 votes 0 votes A) delay due to FF0 is 2ns and the Q0 is clock for FF1 hence clock is divided by 2(because a FF act as frequency divider ) hence 2ns*2=4ns and due to AND gate 1ns and FF2 has 2ns hence total delay 2+4+1+2 ns=7ns frequency =1000/7 =143MHz Neeraj Chandrakar answered Jul 25, 2017 Neeraj Chandrakar comment Share Follow See all 0 reply Please log in or register to add a comment.