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$S_1$: When the write-through protocol used in the simultaneous access memory organization then the hit ratio for write request is 100%.
$S_2$: Conflict and Inference misses can be reduced by double the associativity of a cache design.
$S_3$: In the write back protocol coherence is not present. So inclusion is always a success.
$S_4$: Replacement algorithms are required in the direct, associative and set associative cache designs to replace the cache blocks.
Which of the following is false?
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$S_1$: When the write-through protocol used in the simultaneous access memory organization then the hit ratio for write request is 100%.

When we use write-through protocol, we write the data to the cache as well as to the main memory simultaneously. This ensures that the main memory always contains the updated data. But this increases the average memory time for write operation. This statement is ambiguous, as here "hit ratio" for what? cache or main memory? Assuming it is for cache, then we can't say that we will always have a hit, as the block may or may not be present. So, I think it should be FALSE. Moreover, hit ratio for a write operation in write through cache is meaningless. Since in either a hit or a miss, we need to update the main memory.


$S_2$: Conflict and Inference misses can be reduced by double the associativity of a cache design.

There is nothing like "interference" miss. It should be "inference" miss. Which is same as conflict miss, or collision miss. And yes, conflict misses can be reduced if we increase the associativity of the cache. At the extreme case, if we set the cache to be fully associative, then there will be no conflict miss, only compulsory and capacity misses. So, TRUE.

$S_3$: In the write back protocol coherence is not present. So inclusion is always a success.

Coherence means that the contents of cache and main memory is consistent, i.e. both contains same data. When we use write back policy, the cache may not be coherent with the main memory all the time. This is what we know as "cache coherency problem". So, first part is true (i.e. coherence may not be there). Inclusion means that whatever is in the cache is also on the main memory. If, in any case a block is removed from main memory, must also be removed from the cache. I don't know how they are relating writing policy with the inclusion of cache.


$S_4$: Replacement algorithms are required in the direct, associative and set associative cache designs to replace the cache blocks.

We don't require a replacement algorithm for direct mapped cache, since every block has a fixed mapping in the cache. So, either that slot be empty(so no replacement required), or it might be occupied(so it needs to be replaced). So, this is FALSE.

P.S. This is made easy test series question and here is the solution given by them:

$S_3$ and $S_4$ are false.

Please comment what should be correct ?

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