# MadeEasy Subject Test: CO & Architecture - Dma

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cpu time consumed =trabsfer time of data /trabsfer time + preparation time of data

normally in cycle steling mode 1 byte is transffered but in questin,we are trabsferring 64 bytes=8 words (1 word = 8 bytes)in one cycle time.

so,time for transferring 8 bytes is 8 us.

cycle time of processor is 2us

so, 2/(8 + 2 ) * 100

is this correct?
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I think it should be 25%

Processor bus speed is 4MBps.

Now, I think if pipelining takes place, then I consume 1MBps speed out of 4MBps which is 25%

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nopes answer is 20% only I guess
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I am getting 25%...

to accumulate 64B time would be 64us by the hard disk..32 processor cycles

after 32 cycles processor takes 8 cycles to transfer data to memory.

So processor transfer in 8 cycles after every 32 cycles

8/32*100 should be the answer
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although answer is 20%
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@Vaishali.

I think we are wrong. 20% is correct I think. FOllowing is my argument.

1. Device readies the buffer. When this happening, CPU is utilizing the bus.

2. When buffer is full, only then CPU is interrupted. Then the data transfer takes place. After this, the buffer becomes empty.

The above cycle repeats.

In burst mode, bus is tied up in accordance with the device transfer speed.

In cycle stealing mode, only when buffer is full, bus is seized. This is done to to save bus cycles if the device transfer speed is less as compared to bus speed.

See here for actual difference between steal and burst mode.

It is cycle stealing mode, we assume with the formula x/y

Data is transferred word by word from DMA to memory .

Here total data size in Buffer is 64 Bytes .  And 1 word = 64 bits is given , 64 bits = 8 Bytes

so for 64 B data we need to transfer 8 words means 8 times bus access is require by DMA. [  word size is 64 bit which is 8 byte hence to transfer 64 byte from CPU to MM, DMA has to steal the bus 8 times according to question because here in one time 8 byte will be transferred instead of 1 byte ]

each cycle time is 2  micro second, to transfer 64 Bytes it takes  8 * 2 =16 micro seconds

so Data preparation time is 16 microseconds .

Disk is sending 10 6 in 1sec

so 1 byte is sent in 1 microsec

for 64 byte it will be 64 microsec

it is cycle stealing so total time is 64 ms only as overlapping is happening ..

CPU efficiency = (16/64 ) * 100  = 25 %

so 25% of cpu time is consumed due to DMA activity .

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@Bikram Sir

DMA operation happen on 2 phase

chip configuration phase and data transfer phase.

And also IO operation is part of DMA operation. So, it must be calculated.

http://textofvideo.nptel.iitm.ac.in/106106092/lec26.pdf

CPU time calculated separately while calculating data transfer time

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@srestha

there are 2 phases that generally mention in every qstn. But here in this qstn it is not mentioned..

I/O is preparing data when data is being transferred to CPU, yes it is correct. But data transfer rate is very less by I/O as compared to bus transfer rate. So we can ignore it here...
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@ sir @maam

DMA has to steal the bus 8 times according to question because here in one time 8 byte will be transferred instead of 1 byte ]

each cycle time is 2  micro second, to transfer 64 Bytes it takes  8 * 2 =16 micro seconds

DMA has to steal bus 8 times ..hence 8 times BR and BR happens that is only time cpu get consumed right ??

And for 1 steal it is taken 2 micro second does that means 1 BR + BG happens in 1 cycle time of CPU

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@Bikram Sir, Does this mean that the CPU is blocked 25% of the time?
Lets calculate the processor speed.

It can transfer 64 bits in 2 microsec or 4MBps.

Speed at which the buffer of the device is filled = 1MBps.

Now, lets assume time slot of 1 sec.

In that 1 sec, if I dont transfer 1MB that accumulated in device buffer , it will spill.   So, in 1 sec, I need to transfer 1MB to RAM at speed of bus i.e at 4MBps. That comes out as 0.25 sec.

Now, I steal 0.25 sec out of 1 sec   which 25%.

Hence, processor is blocked for 25%
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25% is blocked time not the consumed time, correct?

How can we consumed time nothing is given like interrupt processing time or grant the bus to I/O.
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The buffer size is only 64 bytes ... how are we accumulating 1MB and then transferring? It should transfer at once after 64 bytes get filled.
answer will be 20%

here buffer size is 64 byte so we have 64 bytes of data in buffer

but word size is 64bit which is 8 byte hence to transfer 64 byte from CPU to MM, DMA has to steal the bus 8 times a/c to ques because here in one time 8 byte will be transfered instead of 1 byte

bo total cycle overhead = 8 *2 = 16 microsec

Disk is sending 10^ 6 in 1sec

so 1 byte is sent in 1 microsec

for 64 byte it will be 64 microsec

Total Time = 64+16

=80 microsec

now CPU efficiency = (16/80)*100

=20%
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I think total time should be 64us only, because after 64us disk can do its own work and processor will transfer data

These two things can be done parallelly
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Can some one confirm what is the correct answer ,20 or 25?
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@rahul sarma

25% is correct answer .
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@srestha

he solved some different way ..though i think total time should be 64us only, because after 64us disk can do its own work and processor will transfer data. And considering 64 us ans comes 25% !!!

And yeah he said " Not sure if we should use word size here  as usually cycle stealing mode is per byte ".

In cycle stealing 1 Byte is transfer in 1 cycle ..
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total time means total data transfer time.rt?

So, it requires time to transfer data +CPU time.

But here word length 64 bits never used.

In cycle stealing 1 B require 1 cycle.So, 64 B total data requires 64 cycles.

So, 64 bits word length useless??
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It says says that buffer of cycle stealing modecan be more than 1 byte.So why cant we have 64byte buffer here?As the question says when 64bytes are prepared then they will be transferred?

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@srestha and @rahul

It is cycle stealing mode, they mention in qstn.

buffer size is 64 byte so we have 64 bytes of data in buffer
but word size is 64bit which is 8 byte hence to transfer 64 byte from CPU to MM, DMA has to steal the bus 8 times a/c to ques because here in one time 8 byte will be transfered instead of 1 byte

bo total cycle overhead time = 8 *2 = 16 microsec

Disk is sending 10 6 in 1sec

so 1 byte is sent in 1 microsec

for 64 byte it will be 64 microsec

​​​​​​​it is cycle stealing so total time is 64 ms only as overlapping is happening ..

CPU efficiency = (16/64 ) * 100  = 25 %

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Are you sure that overlapping between DMA preparation and Data transfer between disk and buffer only happens in cycle stealing and not it burst transfer mode.

Because I dont see any reason why overlapping will not happen in burst transfer. if so the formula for burst time will also become x/y and not x/(x+y). ?

Please resolve the query.
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Are you sure that overlapping between DMA preparation and Data transfer between disk and buffer only happens in cycle stealing and not it burst transfer mode.

Because I dont see any reason why overlapping will not happen in burst transfer. if so the formula for burst time will also become x/y and not x/(x+y). ?

@srestha
1 word=64 bit=8 B

64 B=8 word

machine cycle time=2 microseconds => 1 word is transferred from io buffer to memory by cpu in 2 microseconds => data preparation time by cpu 64 B data and io bandwidth is 1MBps

so 64/10^6 seconds = 64 microseconds = transfer time by io device = time to dump data from io device to io buffer

now in cycle stealing mode generally data is transferred byte wise..but here word size is given so we assume data is transferred word wise..which is actually reasonable because IF ARCHITECTURE IS WORD ADDRESSABLE WITH 1 WORD = 8 B then naturally cycle stealing mode has to follow it...

64B data in 64 microseconds

=> 8 word data in 64 microseconds

=> 1 word data in 8 microseconds = this is word transfer time by io to buffer

so % cpu blocked= % cpu time consumed = % time CPU is actually transferring data from io buffer to main memory= (2/8)*100%=25%

in burst mode its ( 2 / (2+8) )*100%=20%>>>>>>>

in burst mode all data is transferred once as a block...so we wait for io to dump all of 64 B data in its buffer which is 64 microseconds

now cpu will fully transfer this data from io buffer to main memory..64 B data meaning 8 word data meaning 8*2 microseconds meaning 16 microseconds..

so 16*100/(16+64) % = 2*100/(2+8) = 20%

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I have gone through these types of questions but I'm unable to understand. how to appraoch these questions? And during the dma transfer, cpu is considered to be idle. before and after that it can do its own work. Where am I wrong?