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3 Answers

1 votes
1 votes

This counter can count 0 to 7 (mod 8 ,without this or two input gate ) . it will count like this  000 001 ......... 101 110 111 .

the question says its a mod 6 counter so with the help of OR gate we can do it . 

whenever MSB and middle significant bit get 1 their corresponding Cvalue get 0 . so if we use OR gate then only for the input value of  0 0 , it produced 0 and the counter gets cleared .

and it look like this  000 001 010 011 100 101 000 001 ..... ( whenever 1st two bit gets 1 its get cleared means when 110 appear immediately C1 C2 C3 goes to 0 ... means 000  )  

1 votes
1 votes

(a) - OR gate

because when the sequence reaches 110 state q' output of the leftmost flipflop(msb bit of the counter as its clock frequency is least as compare to other three flipflops) and q' output of middle flipflop becomes zero and it should be detected.

we need to detect this state 110 and then reset this 2 flipflops because after 110 state the counter should go to state 000 and start counting again.(its a modulo 6 counter)

the output of the 2 input gate should logic 0 as there is a not symbol in the reset of both the gate.if output is 1 the flipflop will not reset as its reset works for logic 0.

so ,110 state will be detected if the two input gate's output is 0 when both of its input has a value 00 which is possible for both the gate  AND gate and OR gate but we should not use and gate as its output will be 0 even if any one of the input is 0(in case when the state of counter is 010,101,100) which will reset the counter (counter will be reset after 010 if we use and gate -->modulo 2 counter)   and in case of OR gate output will be 0 iff all the input is 0.

 

so, the ans is a.) OR gate

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