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In the given counter circuit, the flip flops are having the propagation delay of 2ns and AND gate is having propagation delay of 1ns.

What is the minimum clock rate possible to apply so that clock will work satisfactorily?

A) 143 MHZ

B) 200 MHZ

C) 333MHZ

D) NONE OF THE ABOVE

Please explain the steps too 

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i think its 200Mhz
two flipflops are operated one after the other(we can see o/p of first FF is clock of 2nd FF) and last flipflop one can be operated in parellel to 1st flipflop.(as there is comn clock for 1st and 3rd FF)
Tclock = Tcombi +2*Tflipflop
Tclock= 1+2*2
Tclock=5ns
frequency = 1/5GhZ = 0.2GHZ = 200MHZ
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A) delay due to FF0 is 2ns and the Q0 is clock for FF1 hence clock is divided by 2(because a FF act as frequency divider ) hence  2ns*2=4ns and due to AND gate 1ns and FF2 has 2ns 

hence  total delay 2+4+1+2 ns=7ns

frequency =1000/7 =143MHz

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