Pipeline

Question

The following sequence of instruction is executed in a basic 5 stage pipelined processor (S₁, S₂, S₃, S₄, S₅). Assume that data dependency present in the program is resolved by operand forwarding techniques. Load instruction output present in 4^th stage ALU instruction output is available in 3^rd stage. Assume each stage take 1 cycle.

$I_{1}:ADD R_{0},R_{1},R_{2}$

$I_{2}:LOAD R_{4}, 1(R_{0})$

$I_{3}: ADD R_{5},R_{4},R_{0}$

$I_{4}: ADD R_{6},R_{5},R_{4}$

$I_{5}: ADD R_{7},R_{5},R_{4}$

What is the number of instructions must be inserted to achieve CPI = 1 by using operand forwarding.

Comments

https://gateoverflow.in/69709/pipelining

Answer 1

I1 : R0 <-- R1 + R2

I2 : R4 <-- M(R0)

I3 : R5 <-- R4 + R0

I4 : R6 <-- R5 + R4

I5 : R7 <-- R5 + R4

I/C	1	2	3	4	5	6	7	8	9	10
I1	S1	S2	S3(R0)	S4	S5
I2		S1	S2	S3	S4(R4)	S5
I3			S1	X	S2	S3(R5)	S4	S5
I4				S1	X	S2	S3(R6)	S4	S5
I5					S1	X	S2	S3	S4	S5

In this Instruction Pipeline Result of I1 are store in 3^rd stage S3 but result of I2 are store in 4^th stage S4 in clock cycle 5 and this instruction are immeditely use in next instruction I3 so, One Stall are genreted.

Hence must be Inserted only one independent instruction between instruction I2 and I3.

Comments

I have seen no question assuming MA-EX split phase.

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why we stall in i2 instruction...?

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the result of load instrunction available at fourth stage so we have to wait till then