Test by Bikram | Mock GATE | Test 3 | Question: 41

Question

A $CPU$ supports $4$ interrupts -  $I1 , I2 , I3$ and $I4$. It supports priority of the interrupts. Nested interrupts are allowed if later interrupt has higher priority than the previous one.

During a certain period of time, we observe the following sequence of entry and exit from the interrupt service routine.

 $I1$ start …….  $I2$  start …..  $I2$ end ….  $I4$ start …..  $I3$ start …..  $I3$ end …  $I4$ end .. $I1$  end

What can we infer about the priority interrupt routines from the above sequence?

• A.    $I3 > I4 > I2 ;  I4 > I1$
• B.    $I2 > I1;   I3 > I4 > I1$
• C.   $I1 > I2 > I3 > I4$
• D.   $I4 > I3 > I2 > I1$

Answer 1

In the given sequence I₁ is least priority interrupt as it ends at the last of Interrupt Service Routine. .

I₃ has higher priority than I₄ as it ends before I₄ .

I₂ has higher priority than I₁ .

Option B better describe the priority.