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A CPU manufacturer has two designs $P1$ and $P2$ for a synchronous pipeline processor.

$P1$ has $5$ pipeline stages with execution times of $3$ $ns$, $4$ $ns$, $3$ $ns$, $2$ $ns$, $4$ $ns$ respectively. The design $P2$ has $6$ pipeline stages with an execution time of $3 ns$ each.

The time that can be saved by $P2$ over $P1$ to execute $1000$ instructions is ______ $ns$.
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The formula is :  Tn = ( K + (N-1) ) * Tcp

where Tn = time taken by processor n

Tcp is  time for execution ,

N = number of instructions to execute , 

K = number of pipeline stages 

We have,   Kp2   = 6 [ 3 ns]

 Kp1  = 5 [ 3 ns, 4 ns, 3 ns, 2 ns, 4 ns ] 

given N = 1000 , for  processor P1, Tcp =  max(execution time ) = 4  . For processor P2, Tcp = 3

Tp1 = ( 5 + ( 1000 - 1 ) ) * 4 = (5 + 999) * 4 = 4016

Tp2 = ( 6 + ( 1000 - 1 ) ) * 3 = ( 6 + 999) * 3 = 3015

time that can be saved by p2 over p1 for executing 1000 instructions is = 4016 - 3015 = 1001 ns

Answer:

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