The Gateway to Computer Science Excellence

+25 votes

When two 8-bit numbers $A_{7}...A_{0}$ and $B_{7}...B_{0}$ in 2's complement representation (with $A_{0}$ and $B_{0}$ as the least significant bits) are added using a **ripple-carry adder, **the sum bits obtained are $S_{7}...S_{0}$ and the carry bits are $C_{7}...C_{0}$. An overflow is said to have occurred if

- the carry bit $C_{7}$ is 1
- all the carry bits $\left ( C_{7},...,C_{0} \right )$ are 1
- $\left ( A_{7}.B_{7}.\bar{S_{7}}+\bar{A_{7}}.\bar{B_{7}}.S_{7} \right )$ is 1
- $\left ( A_{0}.B_{0}.\bar{S_{0}}+\bar{A_{0}}.\bar{B_{0}}.S_{0} \right )$ is 1

+25 votes

Best answer

**Answer is (C)**

Overflow is said to occur in the following cases

$$\begin{array}{|c|c|c|} \hline \textbf{C7} & \textbf {C6} &\textbf {Overflow} \\\hline0&0& \text{NO}\\\hline0&1& \text{YES} \\\hline 1&0&\text{YES} \\\hline 1&1&\text{NO} \\\hline \end{array}$$

The $3^{rd}$ condition occurs in the following case A7B7S7', now the question arises how?

$$\begin{array}{|c|c|c|} \hline \textbf{C7} & \textbf {C6}\\\hline \text{A7}&1\\\text{B7}&1 \\ \text{S7}&0 \\\hline \end{array}$$

NOW, $A7=1$ AND $B7=1 S7=0$ is only possible when $C6=0$ otherwise $S7$ would become $1$.

$C7$ has to be $1$ $($$1+1+0$ generates carry$)$

ON similar basis we can prove that $C7=0$ and $C6=1$ is produced by $A7'B7'S7$. Hence, either of the two conditions cause overflow. Hence(**C).**

Why not A? when $C7=1$ and $C6 =1$ this doesn't indicate overflow ($4^{th}$ row in the table)

Why not B? if all carry bits are $1$ then, $C7=1$ and $C6=$1 (This also generates $4^{th}$ row)

Why not D? These combinations are $C0$ and $C1$, the lower carrys do not indicate overflow

+12 votes

Observe one thing, Overflow can occur when we add two negative numbers or two positive numbers. When we add one negative and one positive number, there can't be an overflow.

Now when we add two positive numbers, result should always be positive and when we add two negative numbers, result should be negative, In representation of signed binary numbers, MSB represents sign of number.

1. Now if MSB of both input numbers is 1 (means numbers are negative) but MSB of sum is 0 (means sum is positive) then it means there is an overflow.

2. Similarly, when MSB of both inputs is 0 (means numbers are positive), but MSB of sum is 1 (means sum is negative), then it also indicates overflow.

Statement 1 above indicates, A'_{7}B'_{7}S_{7 }is 1. Statement 2 above indicates A_{7}B_{7}S'_{7 }is 1.

Hence Option C is answer

+4 votes

the solution is ** C)**

if Both A_{7} and B_{7} is 1 then C_{7} will be 1 and S_{7} is 0 means C_{6} is 0 hence **C _{7}.C_{6}'**

if Both A_{7} and B_{7} is 0 then C_{7} will be 0 and S7 is 1 means C_{6} is 1 hence** C _{7}'.C_{6}**

hence combining both we get **C _{7}.C_{6}'+C_{7}'.C_{6}**

which is **C _{7 }XOR C_{6}** which is condition of detecting Overflow

+2 votes

**Answer:** **(C)**

**Explanation:** Overflow indicates that the result was too large or too small to fit in the original data type.

Overflow flag indicates an overflow condition for a signed operation. Signed numbers are represented in two’s complement representation.

The overflow occurs only when two positive number are added and the result is negative or two negative number are added and the result is positive. Otherwise, the sum has not overflowed.

Therefore, a XOR operation can quickly determine if an overflow condition exists. i.e.,

(A7 . B7 )⊕(S7) = (A7 . B7 . S7‘ + A7‘ . B7‘ . S7 = 1

http://www.geeksforgeeks.org/gate-gate-cs-2017-set-1-question-35/

- All categories
- General Aptitude 1.9k
- Engineering Mathematics 7.5k
- Digital Logic 2.9k
- Programming and DS 4.9k
- Algorithms 4.3k
- Theory of Computation 6.2k
- Compiler Design 2.1k
- Databases 4.1k
- CO and Architecture 3.4k
- Computer Networks 4.1k
- Non GATE 1.5k
- Others 1.5k
- Admissions 595
- Exam Queries 576
- Tier 1 Placement Questions 23
- Job Queries 72
- Projects 17

50,645 questions

56,598 answers

195,838 comments

102,143 users