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Consider a two-level cache hierarchy with $L1$ and $L2$ caches. An application incurs $1.4$ memory accesses per instruction on average. For this application, the miss rate of $L1$ cache is $0.1$; the $L2$ cache experiences, on average, $7$ misses per $1000$ instructions. The miss rate of $L2$ expressed correct to two decimal places is ________.
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214 votes
214 votes

Answer = $0.05$.

Assuming there are 1000 instructions for the ease of calculation, which means there are 7 memory reference misses from the L2 cache.

A cache experiences misses with memory references. Thus, it is essential to determine the counts of incoming memory references and the counts of memory references hitting or missing in order to calculate the cache hit rate or miss rate. Upon reading the question, it becomes apparent that the incoming memory references to the L2 cache are unknown, and we must derive this information using the provided L1 cache information.

 

 

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Best explanation found

Since , it is given in question that for 1 instruction it takes 1.4 memory access(ma)

So, for 1000 instr. it will take =1000* 1.4 ma= 1400 ma

Now , it is given for l1 cache miss rate(mr) = 0.1

and since , we know mr=no. of misses/total no. of ma

so, 0.1=no. of misses/1400

thus, no. of misses of l1 =140

As , we know when there is miss in l1 , we search for data in l2

so, now for l2 cache total no. of ma=140, and it is given there is 7 miss

so , mr for l2 cache=7/140=1/20=0.05
22 votes
22 votes
total number of memory reference = 1000 * 1.4 = 1400

reference to l2 cache = .1 * 1400 = 140

now miss rate = 7/140 = .05
20 votes
20 votes

I really think that for an exam as prestigious as GATE, this question is worded very poorly.

the L2 cache experiences, on average, 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is ....

One can argue that it is 7/1000 = 0.007

I.e. per 1000 instructions given to L2, it misses 7 of them.

But the question actually says, per 1000 instructions given to L1L2 ultimately misses 7 of them.

 

So, give L1 1000 instructions

=> 1400 memory accesses

=> Missed 140 memory accesses.

 

These 140 accesses would pe passed through L2 because of the hierarchy, and L2 would miss 7 of them.

So miss rate of L2 = 7/140 = 0.05.

 

PS: If 0.05 wasn't in the official answer key, I'd never have believed it to be the answer. One of the rare poorly worded GATE question.
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