“the L2 cache experiences, on average, 7 misses per 1000 instructions”
i think this is where everyone is getting the doubt lets approach like how most of u might look at this question…
1.4 memory accesses per instructions , lets assume the processor is executing 1 instruction right now
now for L1 cache miss rate is 0.1 given
$memory\: accesses \, \times global\:miss\:rate\:of \:L1 \:cache = number\: of \:misses \:in \:L1 \:cache$
1.4 X 0.1 = number of misses in L1 cache
number of misses in L1 cache = 0.14
now misses for L1 cache = memory access of for L2 cache
Its given 7 misses per 1000 instructions for L2 cache
so misses per instruction = $\frac{7}{1000}$
$memory\: accesses \:per\:instruction\:for \:L2\:cache \, \times local\:miss\:rate\:of \:L2 \:cache = number\: of \:misses \:in \:L2 \:cache\:per\:instructions$
0.14 X local miss rate of L2 cache = $\frac{7}{1000}$
$\therefore$ local miss rate of L2 cache = $\frac{7}{1000\times 0.14}$ = $0.05$