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Consider a two-level cache hierarchy with $L1$ and $L2$ caches. An application incurs $1.4$ memory accesses per instruction on average. For this application, the miss rate of $L1$ cache is $0.1$; the $L2$ cache experiences, on average, $7$ misses per $1000$ instructions. The miss rate of $L2$ expressed correct to two decimal places is ________.

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+13

Although the question should have been more specific when they talk about L2 miss(7 miss per 1000 instruction) but still 0

I can't understand one thing.

7 misses per 1000 instructions

this 7 misses, we should take it as Global Miss Rate or Local Miss Rate.

Here doing 7/140 means qsn is saying about Global miss rate.

But incase of local miss rate,

$\frac{7*140}{1400}$

Answer = $0.05$. by
edited
+2
how 1000 instructions from cpu to L1 ??
0
Actually is the 1400 Mem access request to L1 . I have showed 1000 instruction as in the question.
0

I M NOT getting .... 1.4 mem ref was given u hv done 1400... i m not getting anything..

OK...i got 1000* 1.4 = 1400

but then from L1 to L2  .. how 140 ???

+26
• An application incurs 1.4 memory accesses per instruction on average & Total instruction are 1000 so total number of memory references = 1.4 * 1000 = 1400
• The miss rate of L1 cache is 0.1  i.e. out of 1400 ,0.1% miss so 1400* 0.1= 140
•  the L2 cache experiences, on average, 7 misses out of 140 miss in cache L1 = 7/140 = 0.5.
1. Note since we are moving toward main memory and secondary memory miss rate is decreases.
2. Miss rate =  number of misses /total number of accesses
+1
Ans is 0.05 and not 0.5 ,right?

@Debashish

miss rate of L2 means, miss rate of L2 instruction w.r.t total instruction in L1 or total instruction in main memory?

As it is given miss rate w.r.t 1000 instruction and u r calculating miss rate w. r. t L1 cache instruction
+5
because only 0.1*1400 = 140 will reach to L2. Because miss rate of L1 is 0.1.
+2
Why we are not making it as 7/1000 as 7 inst are missing out of 1000

So , out of 140 instruction

(7/1000)*140.

+5
Hello krishna

140 are not instructions , they are #of memory accesses.Convert 1000 instructions into # of memory accesses for $L_{2}$ cache , $L_{2}$ cache will only be accesses when there is a miss case for $L_{1}$ cache.
+3
@Krishna 1000 instructions are there out of which total number of memory reference = 1000 * 1.4 = 1400

Now 1400 L1 have miss rate of 0.1 so

reference to l2 cache = .1 * 1400 = 140.  That is 140 instructions are referring L2 cache out of which 7 are miss.

now miss rate = 7/140 = .05
0
The answer is 0.05 not 0.5...
0

in question given .... 7 misses per 1000 instructions

my doubt is....... how do you know that these 7 are memory references misses ?

0
When there is a  memory reference then definitely cache memory is accessed first.. If the word is not present in the cache then it is definitely the case of cache miss...
+4
They are asking Local Miss rate of $L_2$. The Global miss rate for $L_2$=0.005
0
please explain how will we calculate global miss rate

is it 7/1000

and why 0.005
+8
GMR(L2)=7/1400
+2

@vijay kumar 2

Local miss rate=number of misses in a cache divided by number of accesses to that cache

Global miss rate=number of misses in a cache divided by number of memor accesses generated by the processor

For L1 cache, global miss rate=local miss rate.

For L2 cache, global miss rate=Local miss rate of L1 ×Local miss rate of L2

total number of memory reference = 1000 * 1.4 = 1400

reference to l2 cache = .1 * 1400 = 140

now miss rate = 7/140 = .05
Best explanation found

Since , it is given in question that for 1 instruction it takes 1.4 memory access(ma)

So, for 1000 instr. it will take =1000* 1.4 ma= 1400 ma

Now , it is given for l1 cache miss rate(mr) = 0.1

and since , we know mr=no. of misses/total no. of ma

so, 0.1=no. of misses/1400

thus, no. of misses of l1 =140

As , we know when there is miss in l1 , we search for data in l2

so, now for l2 cache total no. of ma=140, and it is given there is 7 miss

so , mr for l2 cache=7/140=1/20=0.05
+2

As , we know when there is miss in l1 , we search for data in l2

Thank you. This clearified my doubt :)

0

Welcome

I really think that for an exam as prestigious as GATE, this question is worded very poorly.

the L2 cache experiences, on average, 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is ....

One can argue that it is 7/1000 = 0.007

I.e. per 1000 instructions given to L2, it misses 7 of them.

But the question actually says, per 1000 instructions given to L1L2 ultimately misses 7 of them.

So, give L1 1000 instructions

=> 1400 memory accesses

=> Missed 140 memory accesses.

These 140 accesses would pe passed through L2 because of the hierarchy, and L2 would miss 7 of them.

So miss rate of L2 = 7/140 = 0.05.

PS: If 0.05 wasn't in the official answer key, I'd never have believed it to be the answer. One of the rare poorly worded GATE question.
0
How to understand, they're asking Global miss rate or Local Miss Rate
0

By default we have to consider local miss rate$=\dfrac{\#\ of\ misses\ in\ cache}{total\ \#\ of\ references\ to\ the\ cache }=\dfrac{7}{140}$

if nothing is specified.

+1 vote
It is given that average references per instruction = 1.4
For 1000 instructions total number of memory references = 1000 * 1.4 = 1400
These 1400 memory references are first accessed in the L1.
Since the miss rate of L1 is 0.1, for 1400 L1 references the number of misses = 0.1 * 1400 = 140
We know when there is a miss in L1 we next access the L2 cache.
So number of memory references to L2 = 140
It is given that there are 7 misses in L2 cache. Out of 140 memory references to L2 cache there are 7 misses.
Hence the miss rate in L2 cache = 7/140 = 0.05
7*100/(1000*1.4) =.5

edited
0
why percentage?
0
yes exactly i also got 0.005 but didnt converted it to percentage..so why percentage when they have not mentioned to input answer in %age?
+1
I dont know why i kept 0.5 in the exam
1.4 memory access per inst so for 1000 inst. we have 1400 memory accesses.

Now,all the 1400 memory accesses will be first to L1 then if there is a miss they will go to L2.

number of memory access on L2 for 1000 instructions = 0.1 * 1400 = 140

miss rate = no. of misses/total no. of memory accesses = 7/140 = 0.05