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ISRO2016-ECE Digital Logic

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For a $10$-bit digital ramp ADC using $500\;\text{kHz}$ clock, the maximum conversion time is

  1. $2048\; \mu \;\text{S}$
  2. $2046\; \mu \;\text{S}$
  3. $2064\; \mu \;\text{S}$
  4. $2084\; \mu \;\text{S}$
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The answer for the above question is

B) 2046uS

Solution:

(2ⁿ-1)*clock speed(2us)=2046uS
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