edited by
711 views
0 votes
0 votes

A half  adder can be constructed using two $2$-input logic gates. One of them is an $\text{AND}$-gate, the other is

  1. $\text{OR}$
  2. $\text{NAND}$
  3. $\text{NOR}$
  4. $\text{EX-OR}$
edited by

1 Answer

Related questions

0 votes
0 votes
2 answers
1
sh!va asked Mar 3, 2017
3,404 views
The sum S of A and B in a half Adder can be implemented by using K NAND gates. The value of K isa) 3b) 4c) 5d) None of these
1 votes
1 votes
1 answer
2
sh!va asked Mar 3, 2017
1,577 views
The combinational logic circuit shown in the given figure has an output Q which isa) ABCb) A+B+Cc)A ⊕ B ⊕ Cd) A. B+C
1 votes
1 votes
1 answer
3
sh!va asked Mar 3, 2017
935 views
The Boolean expression for the output of the logic circuit shown in the figure is$Y=AB+ A'B'+C$$Y= AB+A'B'+ C'$$Y=A B'+ A'B+C$$Y=AB+ A'B+ C'$