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Consider a 4-way set associative cache consisting of 128 lines with a line size of 64 words. The CPU generates a 20-bit address of a word in main memory. The number of bits in the TAG, LINE and WORD fields are respectively:

1. 9, 6, 5
2. 7, 7, 6
3. 7, 5, 8
4. 9, 5, 6
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@Arjun Sir, I guess the correct answer is not in option.  Answer is 9,7,6 ... Because middle one is LINE , not SET ...  for SET we need 5 bits.... but for LINE we need 7 bits.

Number of sets $=\dfrac{\text{cache size}}{\text{(size of a block * No. of blocks in a set)}}$

$=\dfrac{128 * 64}{(64 * 4)}\text{ (4 way set associative means 4 blocks in a set)}$

$= 32.$

So, number of index (LINE) bits $= 5$ and number of WORD bits $= 6$ size cache block (line) size is $64.$

So, number of TAG bits $= 20 - 6 - 5 = 9.$

edited
But in some book answer is option B , as it is asking no of bits in TAG , LINE , WORD which will be 7,7,6 . I am confused which is correct ?
If you are not getting explanation answer does not matter. Also, if GATE books were anywhere near good enough this site would not have been made.
Answer would be 9 7 6

@arjun sir

line here refer to  index offset ?
Sir, middle one is LINE, not SET, so it should be 7... not 5 .... answer is not in option.
How we will know in exam, that line means Index is here?
In my opinion, the word "line" has been used interchangeably as both "block" and "set" in the question, thus raising the ambiguity.
Number of word bits is 6 as explained and number of index bits is 5 which will then produce tag bits to be 20-6-5 = 9. As in set-associative cache mapping the bits are Tag + Index + Word = Address. So even if the line in actual meaning is asked the other values won't change and hence the answer would be 9,7,6 which is not given. So it is a fair assumption that line here is interchangeably used as index.
@Arjun sir, what was given in the official answer keys declared by IITs in 2007?