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The control signal functions of a $4$-$bit$ binary counter are given below (where $X$ is “don’t care”):
$$\small {\begin{array}{|c|c|c|c|l|}\hline
\textbf{Clear}&    \textbf{Clock}&  \textbf{Load}&\bf{ Count}& \textbf{Function}\\\hline
1&\text{X}&\text{X}&\text{X}&\text{Clear to 0} \\
0&\text{X}&0&0&\text{No Change}\\    
0&\uparrow&1&\text{X}& \text{Load Input} \\    
0&\uparrow&0&1& \text{Count Next} \\ \hline  
 \end{array}}$$
The counter is connected as follows:

     

Assume that the counter and gate delays are negligible. If the counter starts at $0,$ then it cycles through the following sequence:

  1. $0, 3, 4$
  2. $0, 3, 4, 5$
  3. $0, 1, 2, 3, 4$
  4. $0, 1, 2, 3, 4, 5$
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Best answer
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48 votes
Whenever  $A4 A3 A2 A1 =0 1 0 1,$ clear line will be enabled as $A3$ and $A1$ are set.

Given table says that whenever clear control signal is set, it clears to $0 0 0 0,$ before the current clock cycle completes.

So, $5$ is cleared to $0$ in the same clock cycle and counter sequence is $0, 1 , 2, 3, 4$

Hence, option C .
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(C) is the correct answer!

$Remark:$
1. If $clear = 1$, counter will be reset to 0000 $\underline{\text{without any delay, and counter doesn't count 5}}$.
2. If $load=1$, counter will be loaded with the input 0011, but note that $\underline{\text{counter counts 5 in this case}}$ unlike clear input.
3. Counter counts from $0$ to $4$.
4. Clear and Load are direct inputs, it means they can be applied to the counter without using any pulse.

 

When the output reaches the count of 1001, both A0 and A3 become 1, making the output of the AND gate equal to 1. This condition activates the Load input; therefore, on the next clock edge the register does not count, but is loaded from its four inputs. Since all four inputs are connected to logic 0, an all‐0’s value is loaded into the register following the count of 1001. Thus, the circuit goes through the count from 0000 through 1001 and back to 0000, as is required in a BCD counter.

In Fig (b), the NAND gate detects the count of 1010, but as soon as this count occurs the register is cleared. The count 1010 has no chance of staying on for any appreciable time, because the register goes immediately to 0.

  1. If $clear=1$, then clear the counter.
  2. If $clear=0, load = 0, count = 1,$ counter counts.
  3. $load = 1,$ loads the input to the counter.

If $load = 1$, then counter will be loaded with $i/p = 0011$

to the given counter, $count = 1, load = 0, clock = \uparrow$

 

$\underline{\text{Note:}}$ If o/p of $\textsf{AND}$ gate is led to $load$, then counter will be loaded with $0011$.

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25 votes
Using the following 2 arguments we can conclude that the counter is Synchronous::

1)

Assume that the counter and gate delays are negligible

If counter delay is assumed to be negligible, then this counter is definately a synchronous counter as in case of asynchronous counter, for an N bit Asynchronous counter, the total propagation delay is N*Tp where Tp is the individual delay of each flip flop involved in counter.

Also, when this is synchronous counter, as soon as the output of bits reaches, 0101, clear logic gets activated and "Assuming no delays" this will quickly make the output appear 0000 and we won't get to see 5 as output of the counter.

To see 5 as the output, either we need to make clear logic work at 6 or we need to add delay to clear logic equal to 1 time period of clock pulse. Till, the next clock pulse comes, just before that our clear logic can be switched on and set counter to 0.

2)

 The output of 0101 from the counter isn't stable. I.E. the output lines of the counter will show 0101 but will immediately be reset to 0. I have drawn this conclusion from the table which states that when clear is 1, the counter will not care about the clock or any other parameter and clear the counter to 0.

I am under the impression that only the stable outputs of a counter can be considered as valid sequences.

 

So, 5 is cleared to 0 in the same clock cycle.

so counter sequence is 0, 1 , 2, 3, 4

Hence option C .
7 votes
7 votes
ans is D:

given input is 0011     

A1 & A3 is 0, so clear=0. now as per last row of table count will be next count. initially counter was 0 now it will become 1.

now 1 will be the input 0001. here A1&A3 is 0, so clear is 0. and again counter will be increased to 2.

now 2 will be the input 0010. here A1&A3 is 0, so claer is 0. and again counter will be increased to 3.

now 3 will be the input 0011. here also A1&A3 is 0. so counter will become 4.

now 4 will be the input 0100. here also A1&A3 is 0. so counter will become 5.

now 5 will be input 0101. here A1&A3 is 1. so clear will become 1. As per first row of table counter will reset to 0 again.

hence ans is D.
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