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+25 votes

The control signal functions of a 4-bit binary counter are given below (where X is “don’t care”):

Clear | Clock | Load | Count | Function |
---|---|---|---|---|

1 | X | X | X | Clear to 0 |

0 | X | 0 | 0 | No change |

0 | $\uparrow$ | 1 | X | Load input |

0 | $\uparrow$ | 0 | 1 | Count next |

The counter is connected as follows:

Assume that the counter and gate delays are negligible. If the counter starts at 0, then it cycles through the following sequence:

- 0, 3, 4
- 0, 3, 4, 5
- 0, 1, 2, 3, 4
- 0, 1, 2, 3, 4, 5

**This question is actually an ambiguous question. How can we decide if it is synchronous counter or ripple counter ? In question they didn't mentioned anything about this..**

Now come to these 2 questions asked in 2015 and 2016 , where they clearly mention synchronous counter https://gateoverflow.in/8054/gate2015-2_7 and https://gateoverflow.in/39670/gate-2016-1-8 and for this 2016 question Both 3 and 4 were given the correct answer in GATE that year by IISC .

This 2007 question should have both C and D as correct answer..

Then why are incrementing a4a3a2a1 from 0000 ? It should be from 0011 right ? Or is the value given just to identify the initial value of clear and then we reset a3a2a1a0 back to 0000 ?

I think , yes , 0011 value given to identify the initial value of clear and then we reset a3a2a1a0 back to 0000 .

@Bikram sir

Using the following 2 arguments can't we conclude that the counter is Synchronous::

1)

Assume that the counter and gate delays are negligible

If counter delay is assumed to be negligible, then this counter is definately a synchronous counter as in case of asynchronous counter, for an N bit Asynchronous counter, the total propagation delay is N*Tp where Tp is the individual delay of each flip flop involved in counter.

Also, when this is synchronous counter, as soon as the output of bits reaches, 0101, clear logic gets activated and "Assuming no delays" this will quickly make the output appear 0000 and we won't get to see 5 as output of the counter.

To see 5 as the output, either we need to make clear logic work at 6 or we need to add delay to clear logic equal to 1 time period of clock pulse. Till, the next clock pulse comes, just before that our clear logic can be switched on and set counter to 0.

So answer here is (C)

2)

the output of 0101 from the counter isn't stable. I.E. the output lines of the counter will show 0101 but will immediately be reset to 0. I have drawn this conclusion from the table which states that when clear is 1, the counter will not care about the clock or any other parameter and clear the counter to 0.

I am under the impression that only the stable outputs of a counter can be considered as valid sequences.

Using the following 2 arguments can't we conclude that the counter is Synchronous::

1)

Assume that the counter and gate delays are negligible

If counter delay is assumed to be negligible, then this counter is definately a synchronous counter as in case of asynchronous counter, for an N bit Asynchronous counter, the total propagation delay is N*Tp where Tp is the individual delay of each flip flop involved in counter.

Also, when this is synchronous counter, as soon as the output of bits reaches, 0101, clear logic gets activated and "Assuming no delays" this will quickly make the output appear 0000 and we won't get to see 5 as output of the counter.

To see 5 as the output, either we need to make clear logic work at 6 or we need to add delay to clear logic equal to 1 time period of clock pulse. Till, the next clock pulse comes, just before that our clear logic can be switched on and set counter to 0.

So answer here is (C)

2)

the output of 0101 from the counter isn't stable. I.E. the output lines of the counter will show 0101 but will immediately be reset to 0. I have drawn this conclusion from the table which states that when clear is 1, the counter will not care about the clock or any other parameter and clear the counter to 0.

I am under the impression that only the stable outputs of a counter can be considered as valid sequences.

@VS

yes, i agree with both of your points.

It is synchronous counter and answer is C.. question is unambiguous too.

yes, i agree with both of your points.

It is synchronous counter and answer is C.. question is unambiguous too.

@VS

If possible, please write a separate answer with all these arguments for this question . Your all points are valid.

If possible, please write a separate answer with all these arguments for this question . Your all points are valid.

@ bharti

0011 value given to identify the initial value of clear and then we reset a_{3}a_{2}a_{1}a_{0} back to 0000

+9 votes

Best answer

(C) is the correct answer!

$Remark:$

1. If clear = 1, counter will be reset to 0000 without any delay, and counter doesn't count 5.

2. If load=1, counter will be loaded with the input 0011, but note that counter counts 5 in this case unlike clear input.

3. Counter counts from 0 to 4.

4. Clear and Load are **direct inputs**, it means they can be applied to the counter without using any pulse.

+19 votes

whenever A4 A3 A2 A1 =0 1 0 1 then clear line will be enabled as A3 and A1 set.

given table says that whenever clear control signal set , it clears to 0 0 0 0 , before the current clock cycle completes.

so 5 is cleared to 0 in the same clock cycle.

so counter sequence is 0, 1 , 2, 3, 4

Hence option C .

given table says that whenever clear control signal set , it clears to 0 0 0 0 , before the current clock cycle completes.

so 5 is cleared to 0 in the same clock cycle.

so counter sequence is 0, 1 , 2, 3, 4

Hence option C .

are you using "Assume that the counter and gate delays are negligible" this line to decide that input is cleared in same clock cylce ?

Yes, as counter is synchronous, it will count 5 too.

In case of asynchronous counter, it counts till 4 only.

Answer should be D.

In case of asynchronous counter, it counts till 4 only.

Answer should be D.

@praveen sir,

i agree with you in general case.

please check the given function table, here clear has highest priority , it will be applied to counter irrespective of clock signal. observer don't cares , when clear set to 1.

i agree with you in general case.

please check the given function table, here clear has highest priority , it will be applied to counter irrespective of clock signal. observer don't cares , when clear set to 1.

we get clear when we reach 0101 is true , but that state won't exist till next clock , before next clock pulse value will be reset to zero , whenever clock applied it goes to 0001 because in the last cycle itself it clear the output of counter to zero.

Praveen sir, I think C should be the answer as the** output of 0101 from the counter isn't stable**. I.E. the output lines of the counter will show 0101 but will immediately be reset to 0. I have drawn this conclusion from the table which states that when clear is 1, the counter will not care about the clock or any other parameter and clear the counter to 0. (also stated by pramod).

I am under the impression that **only the stable outputs of a counter can be considered as valid sequences**. Is this assumption wrong? Please advice.

Since input state is initially given in the question....0011..cant we start from there ?

Like

0011 (3)

0100(4)

0101(5) --> Clear set so 0000(0)

So cant v take sequence as 3,4,0 ?

Like

0011 (3)

0100(4)

0101(5) --> Clear set so 0000(0)

So cant v take sequence as 3,4,0 ?

Assume that the counter and gate delays are negligible

If counter delay is assumed to be negligible, then this counter is definately a synchronous counter as in case of asynchronous counter, for an N bit Asynchronous counter, the total propagation delay is N*Tp where Tp is the individual delay of each flip flop involved in counter.

Also, when this is synchronous counter, as soon as the output of bits reaches, 0101, clear logic gets activated and "**Assuming no delays**" this will quickly make the output appear 0000 and we won't get to see 5 as output of the counter.

To see 5 as the output, either we need to make clear logic work at 6 or we need to add delay to clear logic equal to 1 time period of clock pulse. Till, the next clock pulse comes, just before that our clear logic can be switched on and set counter to 0.

So answer here is (C)

+7 votes

Using the following 2 arguments we can conclude that the counter is Synchronous::

1)

Assume that the counter and gate delays are negligible

If counter delay is assumed to be negligible, then this counter is definately a synchronous counter as in case of asynchronous counter, for an N bit Asynchronous counter, the total propagation delay is N*Tp where Tp is the individual delay of each flip flop involved in counter.

Also, when this is synchronous counter, as soon as the output of bits reaches, 0101, clear logic gets activated and "Assuming no delays" this will quickly make the output appear 0000 and we won't get to see 5 as output of the counter.

To see 5 as the output, either we need to make clear logic work at 6 or we need to add delay to clear logic equal to 1 time period of clock pulse. Till, the next clock pulse comes, just before that our clear logic can be switched on and set counter to 0.

2)

The output of 0101 from the counter isn't stable. I.E. the output lines of the counter will show 0101 but will immediately be reset to 0. I have drawn this conclusion from the table which states that when clear is 1, the counter will not care about the clock or any other parameter and clear the counter to 0.

I am under the impression that only the stable outputs of a counter can be considered as valid sequences.

So, 5 is cleared to 0 in the same clock cycle.

so counter sequence is 0, 1 , 2, 3, 4

Hence option C .

1)

Assume that the counter and gate delays are negligible

If counter delay is assumed to be negligible, then this counter is definately a synchronous counter as in case of asynchronous counter, for an N bit Asynchronous counter, the total propagation delay is N*Tp where Tp is the individual delay of each flip flop involved in counter.

Also, when this is synchronous counter, as soon as the output of bits reaches, 0101, clear logic gets activated and "Assuming no delays" this will quickly make the output appear 0000 and we won't get to see 5 as output of the counter.

To see 5 as the output, either we need to make clear logic work at 6 or we need to add delay to clear logic equal to 1 time period of clock pulse. Till, the next clock pulse comes, just before that our clear logic can be switched on and set counter to 0.

2)

The output of 0101 from the counter isn't stable. I.E. the output lines of the counter will show 0101 but will immediately be reset to 0. I have drawn this conclusion from the table which states that when clear is 1, the counter will not care about the clock or any other parameter and clear the counter to 0.

I am under the impression that only the stable outputs of a counter can be considered as valid sequences.

So, 5 is cleared to 0 in the same clock cycle.

so counter sequence is 0, 1 , 2, 3, 4

Hence option C .

+5 votes

ans is D:

given input is 0011

A1 & A3 is 0, so clear=0. now as per last row of table count will be next count. initially counter was 0 now it will become 1.

now 1 will be the input 0001. here A1&A3 is 0, so clear is 0. and again counter will be increased to 2.

now 2 will be the input 0010. here A1&A3 is 0, so claer is 0. and again counter will be increased to 3.

now 3 will be the input 0011. here also A1&A3 is 0. so counter will become 4.

now 4 will be the input 0100. here also A1&A3 is 0. so counter will become 5.

now 5 will be input 0101. here A1&A3 is 1. so clear will become 1. As per first row of table counter will reset to 0 again.

hence ans is D.

given input is 0011

A1 & A3 is 0, so clear=0. now as per last row of table count will be next count. initially counter was 0 now it will become 1.

now 1 will be the input 0001. here A1&A3 is 0, so clear is 0. and again counter will be increased to 2.

now 2 will be the input 0010. here A1&A3 is 0, so claer is 0. and again counter will be increased to 3.

now 3 will be the input 0011. here also A1&A3 is 0. so counter will become 4.

now 4 will be the input 0100. here also A1&A3 is 0. so counter will become 5.

now 5 will be input 0101. here A1&A3 is 1. so clear will become 1. As per first row of table counter will reset to 0 again.

hence ans is D.

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