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The control signal functions of a $4$-$bit$ binary counter are given below (where $X$ is “don’t care”):
$$\small {\begin{array}{|c|c|c|c|l|}\hline
\textbf{Clear}&    \textbf{Clock}&  \textbf{Load}&\bf{ Count}& \textbf{Function}\\\hline
1&\text{X}&\text{X}&\text{X}&\text{Clear to 0} \\
0&\text{X}&0&0&\text{No Change}\\    
0&\uparrow&1&\text{X}& \text{Load Input} \\    
0&\uparrow&0&1& \text{Count Next} \\ \hline  
 \end{array}}$$
The counter is connected as follows:

     

Assume that the counter and gate delays are negligible. If the counter starts at $0,$ then it cycles through the following sequence:

  1. $0, 3, 4$
  2. $0, 3, 4, 5$
  3. $0, 1, 2, 3, 4$
  4. $0, 1, 2, 3, 4, 5$
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This is 4bit synchronous counter which works according to the table as described. But how the counter is working is kept hidden(Black boxed). This is a positive edge triggered counter, means it will work only on +ve edge of the clock only (Assuming it because of given ↑ in the clock) and the initial input=0 and count=1, load=0 initially given in the figure. Now check the function table and try to figure out the action of this counter.
The initial input to the counter is 0(A4=0,A3=0,A2=0,A1=0)(given in question if the counter starts with 0), count =1, load=0, clear=A1.A3=0

Now check the function on these inputs.

Function= count next, which will become 1,

similarly, now input to the counter=1(A4=0,A3=0,A2=0,A1=1), count=1, load=0, clear=0

Function= count next which will become 2

similarly then it will count 3 then 4 but

But when counter will increament from 4 to 5(A4=0,A3=1,A2=0,A1=1), the clear=A1.A3=1 so CLEAR=1 and input will be reset immediately to 0 because of negligible delay of the gate and for that enrite clock cycle the counter value will be 0(for a fraction of time it is 5). So the counter counts from 0 to 4.
Answer:

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