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32 votes
32 votes

Consider a pipelined processor with the following four stages:

  • IF: Instruction Fetch
  • ID: Instruction Decode and Operand Fetch
  • EX: Execute
  • WB: Write Back

The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage depends on the instruction. The ADD and SUB instructions need $1$ clock cycle and the MUL instruction needs $3$ clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?
$$\begin{array}{ll} \textbf{ADD} & \text{R2, R1, R0} &&& \text{R2 $\leftarrow$ R1$+$R0} \\  \textbf{MUL} & \text{R4, R3, R2} &&& \text{R4 $\leftarrow$ R3$*$R2} \\   \textbf{SUB} & \text{R6, R5, R4} &&& \text{R6 $\leftarrow$ R5$-$R4} \\   \end{array}$$

  1. $7$
  2. $8$
  3. $10$
  4. $14$
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4 Answers

Best answer
57 votes
57 votes

Answer: option B.
Considering EX to EX data forwarding.

$$\small \begin{array}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline
&\bf{t_1}&\bf{t_2}&\bf{t_3}&\bf{t_4}&\bf{t_5}&\bf{t_6}&\bf{t_7}&\bf{t_8}\\
\hline
\textbf{ADD}&\text{IF}&\text{ID}&\color{green}{\boxed{\text{EX}}}&\text{WB}&&&\\
\textbf{MUL}&&\text{IF}&\text{ID}&\color{green}{\boxed{\text{EX}}}&\text{EX}&\color{blue}{\boxed{\text{EX}}}&\text{WB}\\
\textbf{SUB}&&&\text{IF}&\text{ID}&\color{red}{-}&\color{red}{-}&\color{blue}{\boxed{\text{EX}}}&\text{WB}\\
\hline\end{array}$$

EX to EX data Forwarding:

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3 votes
3 votes
$\begin{array}{|c|c|c|c|c|c|} \hline \textbf {T1} & \textbf {T2} & \textbf {T3} & \textbf {T4} & \textbf {T5} & \textbf {T6} & \textbf {T7} & \textbf {T8}  \\\hline \text{IF}& \text{ID} & \text{EX} & \text{WB} &   &  \\\hline \text{} & \text{IF} & \text{ID} & \text{EX} & \text{EX} & \text{EX}   & \text{WB} & \text{} & \text{}\\\hline && \text{IF}& \text{ID} & \text{} & \text{}  & \text{EX}&\text{WB} \\\hline \end{array}$

There will be operand forwarding between first and second insts and 2nd and 3rd instructions
2 votes
2 votes
Correct answer would be 8 cycles.

ADD:  |IF|ID|EX|WB|

MUL:       |IF|ID|....EX........|WB|

SUB:           |IF|ID|            |EX|WB|
1 votes
1 votes

Since operand forwarding is there, by default we consider the operand forwarding from EX stage to EX stage.

Answer:

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