4.8k views

Consider a pipelined processor with the following four stages:

• IF: Instruction Fetch
• ID: Instruction Decode and Operand Fetch
• EX: Execute
• WB: Write Back

The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage depends on the instruction. The ADD and SUB instructions need $1$ clock cycle and the MUL instruction needs $3$ clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?
$$\begin{array}{ll} \textbf{ADD} & \text{R2, R1, R0} &&& \text{R2 \leftarrow R1+R0} \\ \textbf{MUL} & \text{R4, R3, R2} &&& \text{R4 \leftarrow R3*R2} \\ \textbf{SUB} & \text{R6, R5, R4} &&& \text{R6 \leftarrow R5-R4} \\ \end{array}$$

1. $7$
2. $8$
3. $10$
4. $14$
edited | 4.8k views
+1

1.How do we really know about forwarding stages.

2.For the same question we can get ans 10 also if we take operator forwarding from EX to RD.

+4
always take the best case unless told otherwise.
+1
Thanks...
+1

If question is given as numerical, then what should be our assumption? Split phase or Operand forwarding?

(Split phase will obviously give minimum answer.)

0

Considering EX to EX data forwarding.

$$\small \begin{array}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline &\bf{t_1}&\bf{t_2}&\bf{t_3}&\bf{t_4}&\bf{t_5}&\bf{t_6}&\bf{t_7}&\bf{t_8}\\ \hline \textbf{ADD}&\text{IF}&\text{ID}&\color{green}{\boxed{\text{EX}}}&\text{WB}\\ \textbf{MUL}&&\text{IF}&\text{ID}&\color{green}{\boxed{\text{EX}}}&\text{EX}&\color{blue}{\boxed{\text{EX}}}&\text{WB}\\ \textbf{SUB}&&&\text{IF}&\text{ID}&\color{red}{-}&\color{red}{-}&\color{blue}{\boxed{\text{EX}}}&\text{WB}\\ \hline\end{array}$$

EX to EX data Forwarding:

edited
+1
How can we make ID when prev instruction is executing?I'd is fetching operand ..how is it getting it before completion of execution
+6
@uddipto Wrong value will be fetched during ID phase but will be overwritten by original value during EX phase as the result of the execution phase of previous instruction will be given as input immediately.
0
How wrong value will be updated before execution of 2 instruction?

How you are fetching R4 in 3 instruction before executing it in 2 statement?
+2
@Uddipto @Mandeep
that is the case of operand forwarding occurs
+5

@Arjun sir

here as you told in other questions, since split phase (2 stages in same clock-cycle) cannot be done for       Exe-Exe unlike WB-OF or Exe-OF, we are making Exe of I3 in the 7-th clock-cycle instead of 6-th clock-cycle right ??

+3
yes, exactly
0
@Arjun sir : Although answer would be the same,we can do forwarding from EX->ID stage can't we?
0
This answer cleared up forwarding for me totally. Thanks!
0
@prayas if we do operand forwarding from ex to id then also it is taking same cycle.
+2
Shouldn't ID of I3 be in the 6th cycle instead of 4th? Though the final answer would remain same.
+1
I also think so. ID of I3 should be in 6th cycle as only when the next stage of previous instruction has started can a stage be used by current instruction.
0
@Arjun Sir, ID of I3 will be in the 6th cycle or 4th cycle? Please clarify this.
0
In 4th cycle
0
@Abhishek, This is because we are considering EX to EX operand forwarding? What happened in EX to ID operand forwarding?
0
You are always consider best case .
0
should this mean if nothing is given specific about operand forwarding that will be considered as EX to EX forwarding?
0
Implementing split phase here from EX to ID gives the same answer. But what should be the strategy here?

Op. forwarding EX --> EX or op forwarding with split phase EX --> ID?
0

@ ,always consider with the best case if not mentioned which one is giving less number of clock cycle consider that one.

Correct answer would be 8 cycles.

MUL:       |IF|ID|....EX........|WB|

SUB:           |IF|ID|            |EX|WB|

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