Bits used to represent the address = $\log_2{2^{16}} = 16$
Each cache line size $=64$ bytes; means offset requires $6\text{-bits}$
Total number of lines in cache $= 32;$ means line # requires $5\text{-bits}$
So, tag bits $= 16- 6-5=5$
We have a $2\text{D-array}$ each of its element is of size $=1\text{ Byte};$
Total size of this array $= 50 \times 50 \times 1\text{ Byte}=2500\text{ Bytes}$
So, total number of lines it will require to get contain in cache
$=\dfrac{2500B}{64B} = 39.0625 \approx 40$
Starting address of array $= 1100H = 00010 \ 00100 \ 000000$
The group of bits in middle represents Cache Line number $\implies$ array starts from cache line number $4$,
We require $40$ cache lines to hold all array elements, but we have only $32$ cache lines
Lets group/partition our $2500$ array elements in those $40$ array lines, we call this first array line as $A_0$ which will have $64$ of its elements.
This line(group of $64$ elements) of array will be mapped to cache line number $4$ as found by analysis of starting address of array above.
This all means that among those $40$ array lines some array lines will be mapped to same cache line, coz there are just $32$ cache lines but $40$ of array lines.
This is how mapping is:
$\begin{matrix} 0& A_{28} & \\ 1& A_{29} & \\ 2& A_{30} & \\ 3& A_{31} & \\ 4& A_{0} & A_{32} \\ 5& A_{1} & A_{33} \\ 6& A_{2} & A_{34} \\ 7& A_{3} & A_{35} \\ 8& A_{4} & A_{36} \\ 9& A_{5} & A_{37} \\ 10& A_{6} & A_{38} \\ 11& A_{7} & A_{39} \\ 12& A_{8} & \\ \vdots\\ 30& A_{26} & \\ 31& A_{27} & \end{matrix}$
So, if we access complete array twice we get $=32+8+8+8 = 56$ miss because only $8$ lines from cache line number $4$ to $11$ are miss operation, rest are Hits(not counted) or Compulsory misses(first 32).
Hence, answer is option (C).