Average Access time in Memory Organization

Question

Consider a Processor with two Caches which it can access directly in parallel $L_1$(80% hit rate) and $L_2$(90% hit rate) with access times as 100ns and 200ns respectively. In case of miss in any of those it fetches the data from hard disk $L_3$(100% hit rate) which has a latency of 500ns. What is the average access time($T_{avg}$) of the organization?

Comments

whats the percentage of cache hit or miss ?

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Data Missing

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We have the Hit Rates that relates to Hierarchical Accesses; But not those Hit rates that relates to Simultaneous Accesses.
or we can say this the other way round.

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i think data is sufficient .

Answer 1

it is Simultaneous access method to L1 , L2 ,and  L3 Hierchical  access.

T_avg = 0.8 $\times$ 100 + 0.9 $\times$ 200 + 0.2 $\times$ 0.1$\times$ 500 = 270 nsec

i.e. 1st go to L1 and L2 simultaneously , if hit read, if miss then Read from hard disk  to processor .

Note: here it is not given that data from hard disk comes to cache then processor fetch but given In case of miss in any of those it fetches the data from hard disk L3(100% hit rate) which has a latency of 500ns. i.e. Processor fetch data directly from hard disk, looks unpractical but we have to go with question wording.

Comments

As i tell you don't go by formula, SEE Image

see image with checking miss in L1 , CPU check L2 .  

AMAT=h1*t1+h2*t2.  here (1-h1) done if quetion ask if miss in L1 then go to L2. but in question paralley check in both cache.

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@Prashant,

But in simultaneous also we access in parallel?All the memory levels are accessed in parallel,so i am still not getting why it is having (1-h1) factor?

If there is a miss in L1 then goto L2,then this means hierarchical organization?Can you plz help in understanding this concept

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But he question says if miss is in anyone of these then goto l3.As L1 and l2 not be sending response in same time.So assume L1 response comes and it says that its a miss.Now as per question we should refer L3 but instead we are waiting for L2 response and on miss of that we are going to L3?Please clarify?

Answer 2

its simultaneous access method : l1 , l2 and l3 isn`t simultaneous access

Tavg =

0.8*100 + 0.2* 200 + 0.2 * 0.1* 400 = 128ns

or , you can write like this also 

L1_hit  * L1 + L1_miss * ( L2 * L2_hit + L2_miss  (L3- (L2-L1) +L2) ) 

= 0.8*100 + 0.2 *   ( 200*0.9 + 0.1* ( 500-(100)+200 ) 

= 128 ns

Comments

@Arjun Sir,

As per question "In case of miss in any of those it fetches the data from hard disk L3",So incase of miss in L1,it should goto L3 and not to L2?

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^Yes, that is a bit ambiguous in question. It goes to L3 only if a hit does not happen either in L1 or L2.

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@Arjun Sir, @Lakshman Patel RJIT Sir @Sachin Mittal 1 Sir

From this question my understanding is that,

(1). Since it is not mention that L1 is instruction Cache and L2 is Data Cache, then we don't need to go to L2 Cache in both the cache(Hit or Miss).

If it is Hit in L1 cache then directly fetch the data from it otherwise go to L3 cache to fetch the data (since it is given in the question if it is miss in anyone of L1 or L2 cache then go L3 cache, so don't have to go to L2 cache anyway).

So my answer of this question is 

0.80*100 + 0.20*(100+500) = 220ns

(2). If L1 is instruction cache and L2 is data cache case,  then Hit in L1 we have to go to L2 cache to fetch the data, if there is a miss in L1 cache then first fetch the instruction from L3 cache and then go to L2 cache to fetch the data. If there is miss im L2 cache then fetch the data from L3 cache.

For this my answer would be

0.80*(0.90*200+0.10*(200+500)) + 0.20*(100+500 + .90*200+ 0.10*(200+500)) = 0.80*250 + 0.20*850 = 370ns

Correct me if I am wrong.

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Answer 3

Question is incomplete.Refer to this.Similar kind of problem:http://stackoverflow.com/questions/26461237/average-memory-access-time-formula-and-main-memorys-miss-penalty

Comments

here, we have a hybrid of Multi level Hierarchy and Simultaneous Access.

Answer 4

simultaneous ACCESS METHOD will be used 

L1 and L2 are to be accessed parallel i think the time should be used 200nsec with this time we are able to access both the cache memory.. so,

T_avg= (H1+H2)*T2+(1-H1)(1-H2)(T3)

      =(0.8+0.9)*200+(0.2)*(0.1)*(500)

      =340+10

      =350nsec