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There is an $RISC$ processor which uses pipeline technique. Within the processor, all the arithmetic instructions have the same $CPI$ (cycles per instruction).

Which of the following actions would improve the execution time of an arithmetically intensive program in such a processor?

1. Increasing the clock cycle rate.
2. Disallowing any forwarding in the pipeline.
3. Doubling the sizes of the instruction cache and the data cache without changing the clock cycle time.
1.   II only
2.   I and III
3.   III only
4.   I and II

Please provide an explanation for the 1st statement.

What I think is we cant just increase the clock rate according to our ease, there is a limit to that, which is the maximum stage delay.

And I suppose a pipelined system already takes that into account. Is'nt it?

yes i agree and confused about 1st statement

@Mk Utkarsh

Increasing the clock cycle rate

does that means increasing frequency ==> Time period decreases ==> More instructions per unit time ?

i am confused between I and III, they both seem contrasting to each other how can be both seem true, as one says clock cycle rate inc, so clock cycle time dec and latter says not effecting clock cycle rate.

Increasing the clock cycle rate.

The higher the clock rate, the higher the processor's speed.  So, this would improve execution time.

Doubling the sizes of the instruction cache and the data cache without changing the clock cycle time.

Less miss penalties. So, improved execution time.

Option B