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Question 1:- Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associative
cache. Assume that the cache has a line size of four 32-bit words. Draw a block diagram
of this cache showing its organization and how the different address fields are
used to determine a cache hit/miss.Where in the cache is the word from memory location
ABCDE8F8 mapped?

Question 2:-A computer system contains a main memory of 32K 16-bit words. It also has a 4Kword
cache divided into four-line sets with 64 words per line. Assume that the cache is
initially empty. The processor fetches words from locations 0, 1, 2, . . ., 4351 in that
order. It then repeats this fetch sequence nine more times.The cache is 10 times faster
than main memory. Estimate the improvement resulting from the use of the cache.
Assume an LRU policy for block replacement

My doubt :-

Why is 1st bytes addressable and second is word addressable.Means in first we have 4 4byte words mean 16bytes and then block size=4 butes. But in second we have block size of 64 words but we dont convert it to 64*2bytes for block size.the block size assumed is 64 words and number of bits taken were 6 ?

How can i identify whether we need to convert to byte addressable from word size or not?
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