Consider a pipelined system with these $4$ phases:
FI – Fetch instruction
DA – Decode and calculate address
FO – Fetch Operand
EX- Execute instruction
Each phase requires one clock cycle. There were four instructions in the following program:
$\begin{array}{|l|l|} \hline \text{Load } R1 & \leftarrow M[312] \\ \hline \text{ADD } R2 & \leftarrow R1 + M[313] \\ \hline \text{INC } R3 & \leftarrow R2+1 \\ \hline \text{Store } M[314] & \leftarrow R3 \\ \hline \end{array}$
If there exists pipeline hazards , then the number of clock cycles required to complete the above program is _________