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Which of the following statements is/are correct about hazards?

  1. One way to implement branch prediction is to store the result of a branch condition in a branch target buffer to help guide instruction pre-fetching if the branch is encountered again later.
  2. If a multi-cycle, pipelined processor has N pipeline stages, then structural hazards can be avoided completely if at least N registers are available.
  3. Delayed control transfer involves starting the execution of the instruction after a branch or control instruction, regardless of whether the branch is taken.
  1. III only 
  2. II and III only
  3. I and III only
  4. I, II, and III
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  • I is  true: The branch target buffer stores the previous target address for the current branch.
  • II is false : For any given instruction set architecture implemented on an N-stage pipelined processor, N registers probably is not enough registers to completely prevent structural hazards involving a shortage of register hardware. Besides this, structural hazards can result from less availability of other computational elements, such as ALUs.
  • III is true: Delayed control transfer, also known as delayed branching, is an attempt to match with control hazards.
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