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A cache as everyone knows, stores a copy of data from memory in a fast storage near to CPU. Now, in a system with virtual memory, CPU will be working on logical address and this logical address will be translated to physical address by the memory unit before data is fetched from the main memory. So, if we use the cache before this translation, it will be virtually addressed and if we use cache after this translation, it will be physically addressed.

TLB (which is like a cache for page table) is looked up on to perform virtual-physical address translation. So, in a virtually addressed cache, TLB comes after cache and in a physically addressed cache, TLB comes before the cache.

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