Burst Transfer:-
Total time = Data preparation time + Transfer Time + Bus release control time
Data Preparation time = 32*8/20kbps = 32*8/20*1024 = 1/80 s = (800*10^3)/80 cycles = 10^4 cycles
Data Transfer time = DMA initialization time + DMA transfer time = 12 + Size(Data to be Transferred)/Size(Data Bus) * 4 = 12 + 32/2 * 4 = 12 + 64 = 76 cycles
Bus release control time = Data Unavailable. Hence considered to be 0 cycles
Total time = (10^4 + 76 + 0) cycles = (10^4 + 76)/(800*10^3) s = 0.012595 s = 12.595 ms
Cycle Stealing:-
Total time = Data preparation time + Transfer Time + Bus release control time
Data Preparation time = 32*8/20kbps = 32*8/20*1024 = 1/80 s = (800*10^3)/80 cycles = 10^4 cycles
Data Transfer time:-
Data Initialization time for 1 Byte = 12 cycles
Data Transfer time for 1 byte = 4/2 = 2 cycles
Applying Pipelining concept
For 1st Byte 12+2 = 14 cycles. Now when the 1st Byte is being transferred, we can perform initialization for 2nd Byte
Hence only 10+2 = 12 cycles only needed
14+31*12 = 386 cycles
Bus release control time = Data Unavailable. Hence considered to be 0 cycles
Total time = (10^4 + 386 + 0) cycles = (10^4 + 386)/(800*10^3) s = 0.0129825 s = 12.9825 ms
