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+19 votes
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 Which one of the following is true for a CPU having a single interrupt request line and a single interrupt grant line?

  1. Neither vectored interrupt nor multiple interrupting devices are possible

  2. Vectored interrupts are not possible but multiple interrupting devices are  possible

  3. Vectored interrupts and multiple interrupting devices are both possible

  4. Vectored interrupts are possible but multiple interrupting devices are not possible

asked in Operating System by Veteran (59.5k points)
edited by | 3.2k views
+1
whats the correct answer,,? can i leave this... interrupts ?
0
Arjun sir please comment on this question. Lots of confusion. I think both are possible with daisy chaining approach. right??
+1

Answer is Option C.

6 Answers

+18 votes
Best answer

(C) is the correct answer. We can use one Interrupt line for all the devices connected and pass it through OR gate. On receiving by the CPU, it executes the corresponding ISR and after exec INTA is sent via one line. For Vectored Interrupts it is always possible if we implement in daisy chain mechanism.

Ref : Click Here 

answered by Junior (909 points)
edited by
0
Is C the correct answer? Because there's some confusion in the discussion below and some say its B.
Also do we need to study Daisy Chain for Gate?
0

If only 1 INTR  and multiple devices interrupts at the same time, then first task of the IMR controller to check the source of the interrupt(non-vectored). Once source address is obtained, then it uses it's pre-established priority to grant the access to the highest prioritize requestor device. 

So this answer multiple interrupts possible using 1 INTR line.

For the other part, vectored interrupts possible with 1 INTR. Refer the below video.

+14 votes

Answer is C.
Both Vectored interrupts and multiple interrupting devices are both possible.

You know about parallel & serial connection(Daisy Chain).
Multiple devices are connected serially.

This is how it looks like.

So how it handles multiple interrupts ?
By the way what does it mean by handling multiple interrupts?
It means handling the interrupt from multiple I/O devices, & when two or more devices cause interrupt simultaneously, we want to give priority to High priority I/O.

The way it is implemented is....
Even if one I/O device caused interrupt, we can know it...   but who raised it ?
Interrupt ACK is connected to I/O1  (I/O with Highest priority)
If the interrupt was caused by I/O1 then, it will not forward the signal to I/O2. So we can know it was caused by I/O1.
If it was caused by I/O3, then I/O1 will forward it, I/O2 wil forward it .. So it is caused by I/O3.
So we are checking from highest priority I/O to lowest priority.
If two or more device cause interrupt, then priority will be given to higher priority since ACK moves from highest priority, so it will not forward ACK, & we can know we have to serve it first.

answered by Boss (10.7k points)
+2
using single interrupt line we can obviously handle multiple interrupts using OR gate. And to indentify which device raised interrupt, we can use polling or vectored interrupt, and Now to handle multiple interrupts we can use daily chain.All things are consequences of others.
0
So how vectored interrupts are possible here?How will device sends the vector address?
0
@rahul Sharma

When the device has raised an interrupt and INTA signal reaches it, then it stops the signal from going further. After this, it puts down the INTR signal and sends its vector code to the processor via the data bus.
+10 votes
C. is the right option.

Daisy chain can be used.
answered by Active (3.5k points)
–1
it is b)
0
what's the correct answer at many place B option is given as the right answer.
0
but answer is option B
0
Which one is correct? why is C wrong?
+5 votes

Vectored Interrupts are those interrupts in which an I/O module places it's word(usually it's address or a unique service identifier) on the bus so that the cpu can recognize the respective I/O module.

Using, single interrupt request line and single interrupt grant line, both multiple interrupts and vectored interrupts are possible.

Example : Intel 80386 configured with External Interrupt Arbiter : Intel 82C59A

The below read may be further useful

Source : William Stallings 9ed

So ans- (c)

answered by Boss (11k points)
–4 votes
CPU has single interrupt request and grant line. Here multiple request can be given to CPU but CPU interrupts only for highest priority interrupt so option (A) & (D) are wrong. But here in case of single interrupt lines definitely vectored interrupts are not possible. Hence (B) is correct option.
answered by Junior (643 points)
0
correct answer should be (B)

we use daissy chain suct that multiple devices raise an interrupt and their interrupts are services in a chain one by one

but in vectorred interrupt, only high priority device are served and other requests are masked with the use of masking register such that no other low priority device can interrupt the current device operation
–5 votes
Option b.
answered by Active (3.3k points)
0
Please explain how?
0
I also agree with the single interrupt line vectored interrupt are not possible in daisy chain in serial fashion all interrupted devices are arranged In priority order here devices makes an interrupt by making logic level of interrupt low then thereby cpu responds by making ack line enable however in vectored interrupt in which interrupt ing device directs the processor to appropriate interrupt service routine so according to this b should be answer here
Answer:

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