It is write through, both cache and MMU update at same time.
L1 gives misses 80% of the time. That means L1 gives hit 20% of the time . Memory is accessed 80% of time and cache is accessed 20 % of time.
H = 0.2 , (1- H) = 0.8
T mem update time = 30 ns
TAvg writing Time = H * T mem update time + ( 1 - H ) * ( T mem update time )
= 0.2 * 30 + 0.8 * 30
= 6 + 24
= 30
In write through both cache and MMU update same time that's why only MMU update time is consider here .
So, average writing time is 30 ns .