Consider a 4 stage pipeline with stages named S1,S2,S3,S4. Let I1,I2,I3,I4 be 4 instructions and the number of clock-cycles needed by each instruction in each stage is given below.
The number of clock-cycles needed to complete the instruction cycle of the 4 instructions is ___.
can you please help ...
lemme know if i m wrong......
i am getting this ...please verify
@ Vicky rix
see this http://gateoverflow.in/1314/gate2009-28
we should always assume that the buffer can store more than 1 instruction's data in a queue ??? or in that problem the examiner has assumed like that but generally we take only one instruction's data in buffer ..??? .in hamacher book it is clearly given that we should always take only one instruction's data in a buffer....
@ Bikram sir my doubt is not answer ...
actually in the link you have sent , the problem is solved assuming that a buffer between any 2 stage can hold more than 1 instruction's data at a time ... but is it true always ??? or in that question it was assumed like that ..?? ex : in the diagram
MY DOUBT is whether we should always assume like that ??? generally in books it is given that a buffer can hold only one instruction's data at a time ...
@ Bikram sir
thanks ...now got it ...
@ Saswat Swarup
Stage buffers are used in this question.
Here we assume that a buffer between any 2 stage can hold more than 1 instruction's data at a time .
This is our assumption to match the answer :)
Because if we take single instruction's data in a buffer then no answer matches here . Hope you get my point !
According to me Ur procedure is correct.
X->YZ , Y->XZ , ...