Register

doubt in COA

• retagged by
300 views
1 votes
1 votes

Will a RAW hazard always cause the pipeline to stall ???    NO right ?

Here though we have RAW hazard it doesnot need to stall the pipeline .. right ??? 

• retagged by
User Avatar

Please log in or register to answer this question.

Voting & Accepting an answer helps improve the community
← PreviousNext →
← Previous in categoryNext in category →

Related questions

2 votes
2 votes
2 answers
1
Vicky rix asked Jul 15, 2017
310 views
doubt in coa
is it 5 or 4 ..?? some places i am finding it as 4 (number of cycles) and in some places it is given as 5(number of slots)..please confirm
is it 5 or 4 ..?? some places i am finding it as 4 (number of cycles) and in some places it is given as 5(number of slots)..please confirm
User Avatar
1 votes
1 votes
0 answers
2
Nandkishor3939 asked Jan 19, 2019
776 views
Speedup in coa
In a processor each instruction execution completes in 4 clock cycle with 2.5 gigahertz. The same processor is transformed into a pipelined processor with five stages operated with 2.0 gigahertz what is the speedup achieved.
In a processor each instruction execution completes in 4 clock cycle with 2.5 gigahertz. The same processor is transformed into a pipelined processor with five stages ope...
User Avatar
2 votes
2 votes
1 answer
3
Vicky rix asked Jul 16, 2017
2,621 views
COA problem in pipelining
Consider a 4 stage pipeline with stages named S1,S2,S3,S4. Let I1,I2,I3,I4 be 4 instructions and the number of clock-cycles needed by each instruction in each stage is given below. The number of clock-cycles needed to complete the instruction cycle of the 4 instructions is ___.
Consider a 4 stage pipeline with stages named S1,S2,S3,S4. Let I1,I2,I3,I4 be 4 instructions and the number of clock-cycles needed by each instruction in each stage is gi...
User Avatar
0 votes
0 votes
0 answers
4
Soumya Tiwari asked Nov 16, 2018
177 views
Self Doubt COA
https://gateoverflow.in/63585/pipelining Can anyone Explain the meaning of the line- "Assume that no instruction starts at first stage time the branch condition is evaluated"
https://gateoverflow.in/63585/pipeliningCan anyone Explain the meaning of the line-"Assume that no instruction starts at first stage time the branch condition is evaluate...
User Avatar
Link Copied!