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How to calculate the total gate delay for 16 bit adder using 4, 4 bit CLA?

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in Digital Logic 695 views
it depends on max value of fan-in...

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The delay depends on the Fan in of AND gate used,

i.e If n Bit numbers are added using CLA where k is Fan in of AND gate used, then

T(n) = logk n

Please correct me if i am wrong.


you are correct if there is single CLA
but there are several other factors also to be considered in this qsn, here adder is made up of 4, 4bit CLA...
each CLA can work in logkn time but it has to wait for preceeding CLA to provide carry bit and hence total time taken will be Nlogkn, where N are nos of CLA rippled together...
it can be seen that although each CLA work in parrellel way but they have to wait for preceeding CLA(to provide carry bit which can be used as C0)..
therefore it is hybrid mixture of parrellel and ripple adder..

 Yes, We have to consider the ripple factor N which indicates, How many times a CARRY has to ripple through the adder, since we have 4,4 bit CLA. Since each CLA gets carry from previous CLA, here can we say N=3 ?
as there is no need of ripple carry for first CLA.
Please correct me if iam wrong. Is my understanding correct?
yes, you are correct...

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