The Gateway to Computer Science Excellence
+1 vote
585 views

How to calculate the total gate delay for 16 bit adder using 4, 4 bit CLA?

Question source:https://en.wikipedia.org/wiki/Carry-lookahead_adder

in Digital Logic by Loyal (8.4k points) | 585 views
+1
it depends on max value of fan-in...

1 Answer

0 votes

The delay depends on the Fan in of AND gate used,

i.e If n Bit numbers are added using CLA where k is Fan in of AND gate used, then

T(n) = logk n

Please correct me if i am wrong.

by Active (4.4k points)
0

you are correct if there is single CLA
but there are several other factors also to be considered in this qsn, here adder is made up of 4, 4bit CLA...
each CLA can work in logkn time but it has to wait for preceeding CLA to provide carry bit and hence total time taken will be Nlogkn, where N are nos of CLA rippled together...
it can be seen that although each CLA work in parrellel way but they have to wait for preceeding CLA(to provide carry bit which can be used as C0)..
therefore it is hybrid mixture of parrellel and ripple adder..

0
@joshi_nitish,
 Yes, We have to consider the ripple factor N which indicates, How many times a CARRY has to ripple through the adder, since we have 4,4 bit CLA. Since each CLA gets carry from previous CLA, here can we say N=3 ?
as there is no need of ripple carry for first CLA.
Please correct me if iam wrong. Is my understanding correct?
0
yes, you are correct...

Related questions

0 votes
0 answers
1
asked May 14, 2016 by tamnna (5 points) | 696 views
+1 vote
2 answers
4
Quick search syntax
tags tag:apple
author user:martin
title title:apple
content content:apple
exclude -tag:apple
force match +apple
views views:100
score score:10
answers answers:2
is accepted isaccepted:true
is closed isclosed:true
50,737 questions
57,306 answers
198,314 comments
105,010 users