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Consider a three word machine instruction

$\text{ADD} A[R_0], @B$

The first operand (destination) $“A[R_0]”$ uses indexed addressing mode with $R_0$ as the index register. The second operand (source) $“@B”$ uses indirect addressing mode. $A$ and $B$ are memory addresses residing at the second and third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During execution of $\text{ADD}$ instruction, the two operands are added and stored in the destination (first operand).

The number of memory cycles needed during the execution cycle of the instruction is:

1. $3$
2. $4$
3. $5$
4. $6$

edited ago

$M[A+[R_{0}]]\leftarrow M[A+[R_{0}]]+M[[B]]$

 $IF$ $ID$ $OF$ $PD$ $WB$ $s1$ $s2$ $1MR$ $2MR$ $1RR,$ $1ALU,$ $1MR$ $2MR$ $1ALU$ $1RR,$ $1ALU,$ $1MR$

option B) 4 is correct

$1\;\text{memory read}$ to get the first operand from memory address $A+R_0\; (A$ is given as part of instruction)
$1\;\text{memory read}$ to get the address of the second operand (since second uses indirect addressing)
$1\;\text{memory read}$ to get the second operand from the address given by the previous memory read
$1\;\text{memory write}$ to store to first operand (which is the destination)

So, total of $4$ memory cycles once the instruction is fetched.

The second and third words of the instruction are loaded as part of the Instruction fetch and not during the execute stage.
Reference: http://www.cs.iit.edu/~cs561/cs350/fetch/fetch.html

by

How A is given as  part of instruction?

This is a snippet from the morris mano book, When A(X) is given A is automatically the base address and X is the offset/index.

@Shubhodeep Thanks!

indirect addressing mode will take 2 memory cycles and A[R0] will take 1  memory cycles... Total 4 memory cycles .. Here equation is  A[R0] = A[R0] + @B ...  where A and B are memory addresses ...  A[R0] will be interpreted as A+M[R0] which will produce a memory address ... so 1 memory cycle for it .. So Total 1+1+2 = 4 ...

1 comment

This interpretation is totally incorrect and according to this approach  the answer should be 3..

You'll find that the address of the register where the offset is stored is given, and that doesn't require a memory cycle to fetch....

B) as Memory[ A+R0 ]<--Memory[ A+R0 ] + Memory[memory[B]]

Memory[A] is given as part of the instruction.

Sir ,Which line indicates that Mem[A] is part of inst. i am not able to get this :/
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@kalpish

thiz one The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes

A TOTAL OF 6 MEMORY ADDRESS NEED TO BE ACCESSED TIN ORDER TO PERFORM THE INSTRUCTION.

THE ABOVE CODE CONTAINS 3 PARTS:

3. ARITHMETIC OPERATION / STORE RESULT ADD

1. A[R0] RESULTS IN 3 MEMORY ACCESS

A[R0] = A + (R0)

A[R0] IS  A TYPE OF DISPLACEMENT ADDRESSING MODE IN WHICH THE FINAL MEMORY [A+R0] IS ACCESSED BY ADDING THE BASE ADDRESS "R0" TO THE DISPLACEMENT ADDRESS "A"

2. @B FETCHED THE OPERAND IN 2 MEMORY ACCESS SINCE IT IS AN INDIRECT ADDRESSING MODE.

3. ONE MORE MEMORY ACCESS IS REQUIRED IN ORDER TO STORE THE FINAL ADD RESULT IN THE DESTINATION ADDRESS.

A TOTAL OF 6 MEMORY ADDRESS NEED TO BE ACCESSED TIN ORDER TO PERFORM THE INSTRUCTION.

1 comment

@arjun Sir

Execution Cycle contains - ID( instruction decode), Operand Fetch, Process Data(ALU) +Write Back(if any)

total of 6 cycles are needed to execute this.

Decode Phase - 2 Memory Reference

Operand fetch phase -

for 2nd Source (@B)  - 2 memory reference to get data

for 1st Source(A[r0]) - 1 memory reference to get data

Write back phase ( A[r0) <- A(r0) + @B) - 1 memory reference to write data at memory location pointed by (A+r0) address

So total of 6 memory reference in execute cycle.

Please explain how 4 Memory references  are needed in this?