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Consider a three word machine instruction

ADD A[R0], @B

The first operand (destination) “A[R0]” uses indexed addressing mode with R0 as the index register. The second operand (source) “@B” uses indirect addressing mode. A and B are memory addresses residing at the second and third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During execution of ADD instruction, the two operands are added and stored in the destination (first operand).

The number of memory cycles needed during the execution cycle of the instruction is:

  1. 3
  2. 4
  3. 5
  4. 6
asked in CO & Architecture by Veteran (69k points)
retagged by | 4.3k views

thiz is right answer

consider thiz The number of memory cycles needed during the execution cycle of the instruction is:

nd solve u reach 4 as answer

Refer  Heading -> 3. Two address instructions  in http://www.cs.iit.edu/~cs561/cs350/fetch/fetch.html.

@Arjun sir @Bikram Sir is everything correct here ?https://www.cs.umd.edu/class/sum2003/cmsc311/Notes/CompOrg/fetchDecode.html

@junaid ahmad 

is everything correct here ?

No. refer @reena_kandari's comment in selected answer.

@Chhotu Can you mention specifically what's wrong in here .
i dont think something is wrong in his diagram ..

http://www.cs.iit.edu/~cs561/cs350/fetch/fetch.html 

@Arjun sir this link has a mistake actually in 2 and 3 address instructions once we fetch the instruction MAR points to the first word of the instruction and then as we increment MAR by 1 we get the NEXT INSTRUCTIONS ADDRESS we dont get the operands address directly hence we need to fetch those extra two words into temporary registers and then further fetch the operands present in those addresses into the registers 

A link is not working. please update it @junaid ahmad 

3 Answers

+59 votes
Best answer

1 memory read - get first operand from memory address A+R0 (A is given as part of instruction)
1 memory read - get address of second operand (since second uses indirect addressing)

1 memory read - to get second operand from the address given by the previous memory read

1 memory write - to store to first operand (which is the destination)

So, totally 4 memory cycles once the instruction is fetched.

The second and third words of the instruction are loaded as part of the Instruction fetch and not during the execute stage:
Ref: http://www.cs.iit.edu/~cs561/cs350/fetch/fetch.html

answered by Veteran (346k points)
selected by

 

Refer -> http://www.cs.uwm.edu/classes/cs315/Bacon/Lecture/HTML/ch05s06.html

Decode instruction: Hardware determines what the opcode/function is, and determines which registers or memory addresses contain the operands (It may be immediate, direct or indirect etc. )

Refer -> http://www.cs.iit.edu/~cs561/cs350/fetch/fetch.html

addresses of the memory operands are loaded.

So till ID phase we know that what is the instruction(here ADD) and what are operands of the instruction (here A, $R_{0}$ and B). Now in OF(Operand Fetch) phase. Based on information provided by ID phase actual data(like $T_{0}  \leftarrow mem[ A+R_{0} ]$ and $T_{1} \leftarrow mem[mem[B]] $) is loaded in the respective registers(Effective Address calculation also happens in this phase).

OF phase may take 0 or more cycle based on operands are immediate, direct, indirect etc.

  1. IF
  2. ID
  3. OF
  4. EX
  5. WB 

Now in selected answer  3 to 5 is considered as execution cycle of the instruction so answer is 4 (https://www.slideshare.net/utsav_shah/instruction-execution-cycle).

I hope this helps. Please correct me if anything is incorrect. 

 

" The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes 

 

what is meant by this line ?

@sushmita Exactly that :)

An instruction can be of multiple words and here the first word says everything except the operands.
had it been total cycles needed, we would have to count register references too right? So the answer would have been 6 ?
@Just_bhavana , Register access time is much less than memory access time hence it is not counted..

If it were asked  "no of memory cycles needed for decode and execute phase"..Then in decode phase , we access the second and third word of instruction..So total cycles needed in decode and execute phase = 4 + 2 = 6.
Thanks for the explanation @Habibkhan
but how the remaining 2 words of instruction is fetched

I've updated the image shared by @reena_kandari. Please add this image to the answer to avoid further confusion.

@Chhotu here first the instruction is fetched in fetch phase and the opcode is decoded in the decode phase and then we come where the operands are present after DECODING and then we fetch the operands in OPERAND FETCH PHASE as here this phase is absent we merged it with EXECUTION PHASE hence we need 4 cycles as @Arjun sir specified https://gateoverflow.in/user/Chhotu

I think, This is clearly $CISC$ architecture, So we include write back in execution step. But Had it been $RISC$ then we wouldn't have included write back in execution.

$5$ stages story is primarily of $RISC$ only.
+3 votes
B) as Memory[ A+R0 ]<--Memory[ A+R0 ] + Memory[memory[B]]
answered by Boss (6.9k points)
edited by

 Memory[A] is given as part of the instruction. 

Sir ,Which line indicates that Mem[A] is part of inst. i am not able to get this :/
@kalpish

thiz one The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes
+1 vote
indirect addressing mode will take 2 memory cycles and A[R0] will take 1  memory cycles... Total 4 memory cycles .. Here equation is  A[R0] = A[R0] + @B ...  where A and B are memory addresses ...  A[R0] will be interpreted as A+M[R0] which will produce a memory address ... so 1 memory cycle for it .. So Total 1+1+2 = 4 ...
answered by Veteran (23.9k points)
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