Consider a three word machine instruction
ADD A[R0], @B
The first operand (destination) “A[R0]” uses indexed addressing mode with R0 as the index register. The second operand (source) “@B” uses indirect addressing mode. A and B are memory addresses residing at the second and third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During execution of ADD instruction, the two operands are added and stored in the destination (first operand).
The number of memory cycles needed during the execution cycle of the instruction is:
thiz is right answer
consider thiz The number of memory cycles needed during the execution cycle of the instruction is:
nd solve u reach 4 as answer
Refer Heading -> 3. Two address instructions in http://www.cs.iit.edu/~cs561/cs350/fetch/fetch.html.
@Arjun sir @Bikram Sir is everything correct here ?https://www.cs.umd.edu/class/sum2003/cmsc311/Notes/CompOrg/fetchDecode.html
is everything correct here ?
is everything correct here ?
No. refer @reena_kandari's comment in selected answer.
@Arjun sir this link has a mistake actually in 2 and 3 address instructions once we fetch the instruction MAR points to the first word of the instruction and then as we increment MAR by 1 we get the NEXT INSTRUCTIONS ADDRESS we dont get the operands address directly hence we need to fetch those extra two words into temporary registers and then further fetch the operands present in those addresses into the registers
A link is not working. please update it @junaid ahmad
1 memory read - get first operand from memory address A+R0 (A is given as part of instruction)
1 memory read - get address of second operand (since second uses indirect addressing)
1 memory read - to get second operand from the address given by the previous memory read
1 memory write - to store to first operand (which is the destination)
So, totally 4 memory cycles once the instruction is fetched.
The second and third words of the instruction are loaded as part of the Instruction fetch and not during the execute stage:
I've updated the image shared by @reena_kandari. Please add this image to the answer to avoid further confusion.
@Chhotu here first the instruction is fetched in fetch phase and the opcode is decoded in the decode phase and then we come where the operands are present after DECODING and then we fetch the operands in OPERAND FETCH PHASE as here this phase is absent we merged it with EXECUTION PHASE hence we need 4 cycles as @Arjun sir specified https://gateoverflow.in/user/Chhotu
@arjun sir , 2nd and 3rd word of the instruction only known after decoding the opcode fetched in instruction fetch , then decode fetch must be comes under executuion phase , then 2 extra mr will make 6 memory references, here i m sharing the carl hamachar line in which in fetch cycle only instruction is loaded in instruction register ,
Memory[A] is given as part of the instruction.
The answer to the first question is $2048 ...