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Consider a three word machine instruction

$ADD A[R_0], @B$

The first operand (destination) “$A[R_0]$” uses indexed addressing mode with $R_0$ as the index register. The second operand (source) “[email protected]$” uses indirect addressing mode. $A$ and $B$ are memory addresses residing at the second and third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During execution of $ADD$ instruction, the two operands are added and stored in the destination (first operand).

The number of memory cycles needed during the execution cycle of the instruction is:

  1. $3$
  2. $4$
  3. $5$
  4. $6$
in CO and Architecture
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0

thiz is right answer

consider thiz The number of memory cycles needed during the execution cycle of the instruction is:

nd solve u reach 4 as answer

1

Refer  Heading -> 3. Two address instructions  in http://www.cs.iit.edu/~cs561/cs350/fetch/fetch.html.

16

@Arjun sir @Bikram Sir is everything correct here ?https://www.cs.umd.edu/class/sum2003/cmsc311/Notes/CompOrg/fetchDecode.html

0

@junaid ahmad 

is everything correct here ?

No. refer @reena_kandari's comment in selected answer.

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@Chhotu Can you mention specifically what's wrong in here .
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i dont think something is wrong in his diagram ..
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http://www.cs.iit.edu/~cs561/cs350/fetch/fetch.html 

@Arjun sir this link has a mistake actually in 2 and 3 address instructions once we fetch the instruction MAR points to the first word of the instruction and then as we increment MAR by 1 we get the NEXT INSTRUCTIONS ADDRESS we dont get the operands address directly hence we need to fetch those extra two words into temporary registers and then further fetch the operands present in those addresses into the registers 

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A link is not working. please update it @junaid ahmad 

0
@junadahmed the depiction of stages is wrong, as the effective address calculation and ALU operation is performed in the EX stage rather than OF stage, operands are fetched in ID stage itself and the address calculation after the operands are fetched is done through the ALU unit available in the EX stage, see the MULTICYCLE and SINGLE CYCLE implementation of DATA PATH in a CPU.
2
Any conclusions regarding the final answer. I strongly think that the answer has to be 6. 2MR for ID, 1RR & 1MR for source 1, 2 MR for source 2, 1 ALU to process data, 1 MR to WB.

So finally 6 MR should be there. Please let me know if I am wrong.
0
IF FOR the SAME QUESTION, Addressing modes are changed then what will be answer.

Assume 1st operand is fetched using Direct addressing Mode and 2nd using Indirect.
0
Direct addresing required one memory cycle & indexed addressing also required one cycle so answer should be same
0

What if this line wouldn't have been there.

During execution of ADD instruction, the two operands are added and stored in the destination (first operand).

Now the answer must change to 3 cycles right??

Because in the $\textbf{memory access phase}$ the content of execution phase must be written to the memory

1

$M[A+[R_{0}]]\leftarrow M[A+[R_{0}]]+M[[B]]$

$IF$ $ID$ $OF$   $PD$ $WB$
    $s1$ $s2$    
$1MR$ $2MR$ $2MR$ $1RR,$ $1ALU,$ $1MR$ $1ALU$ $1RR,$ $1ALU,$ $1MR$

 

0
option B) 4 is correct

6 Answers

105 votes
 
Best answer

$1$ $\text{memory read}$ to get first operand from memory address $A+R_0$ ($A$ is given as part of instruction)
$1$ $\text{memory read}$ to get address of second operand (since second uses indirect addressing)
$1$ $\text{memory read}$ to get second operand from the address given by the previous memory read
$1$ $\text{memory write}$ to store to first operand (which is the destination)

So, totally 4 memory cycles once the instruction is fetched.

The second and third words of the instruction are loaded as part of the Instruction fetch and not during the execute stage.
Reference: http://www.cs.iit.edu/~cs561/cs350/fetch/fetch.html

 

Correct Answer: $B$


edited by
0
but how the remaining 2 words of instruction is fetched
2

I've updated the image shared by @reena_kandari. Please add this image to the answer to avoid further confusion.

0

@Chhotu here first the instruction is fetched in fetch phase and the opcode is decoded in the decode phase and then we come where the operands are present after DECODING and then we fetch the operands in OPERAND FETCH PHASE as here this phase is absent we merged it with EXECUTION PHASE hence we need 4 cycles as @Arjun sir specified https://gateoverflow.in/user/Chhotu

0
I think, This is clearly $CISC$ architecture, So we include write back in execution step. But Had it been $RISC$ then we wouldn't have included write back in execution.

$5$ stages story is primarily of $RISC$ only.
0
good explanation @habib khan
0

@arjun sir , 2nd and 3rd word of the instruction only known after decoding the opcode fetched in instruction fetch , then decode fetch must be comes under executuion phase , then 2 extra mr will make 6 memory references, here i m sharing the carl hamachar line in which in fetch cycle only instruction is loaded in instruction register , 

0
@saket nandan

Yeah,in Carl hamacher it's direct written that fetching operands from memory or processor registers are to be counted under instruction execute phase.

And there are only 2 phases- instruction fetch(which is only fetching instruction from memory) and second is instruction execute, which is everything left to do.

 

So operand fetch is under instruction execute.

Accordingly, 6 cycles are needed.
0
Instruction decode phase is part of Fetch Cycle.

Source-Hamacher 5th edition pg 412,413 under heading 7.1 "Some fundamental concepts"
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@Ayush Upadhyaya

just read the last paragraph(till the last last line of that paragraph) of page 43 of the same book you've mentioned completely.
2
In cases where an instruction occupies more than one word

Step 1: Fetch the contents of the memory location pointed to by PC.

Step 2: Increment PC by one word

both above steps must be repeated as many times as necessary to fetch the complete instruction. These two steps are usually referred to as the fetch phase.

Step3:(Execution Phase)Carry out actions specified by the instruction in the IR.

Where I went wrong?
3
@Ayush Upadhyaya

you seems right and the answer should be 4. and answer is 4 not because decode step is considered in the fetch cycle but due to the fact that the given instruction is 3 word instruction and 2nd and 3rd words are the addresses A and B respectively, so no need for further decode step. had it been given that the instruction is single word, then the answer would be 6. what do you think? am i right?
0
But, even if the instruction is of 3 words and in 1 machine cycle CPU can fetch only one word, how can the cpu continue with execution of an instruction which has not been completely fetched.So, 2 more machine cycles are required for fetching instruction completely.
0

@aambazinga i am completely agree with you.

0
According to me , the answer should be 3 because calculating the effective address doesnot comes under the execute phase . Execute phase includes operand fetching and execution.

Three memory cycles  :

Fetch Phase :

T0 : AR <-PC

T1 : IR <- AR // Whole of the three words gets loaded into IR here

Decode Phase :

T2 : TR <- IR (part of IR containing starting base address of array A)

T3 : AR <- IR (Load AR with the part of IR containing indirect address )

Calculating Effective Address :

T4: AR<- M[AR] // One memory access for calculating effective address ie address to operand

T5 : TR <- TR +R0(index register) // here we calculated effective address for indexing

Execute Phase (Fetching Operands and execution)

T6: DR <- M[AR] // Fetching second operand , memory access

T7 : AC <- DR // Moving fetched operand into accumulator

T8 : AR<- TR // Moving address present into temporary register to address register

T9: DR <- M[AR] // Fetching the first operand , memory access

T10 : AC <- DR + AC

T11 : M[AR] <- AC // Putting operand back into the memory , memory access

If I am wrong please correct me
0
For all comments, clearing my doubt +10!
0
nice explanation
0

Can anyone help me in Understanding, What exactly does "Memory Cycle" mean?

0

@ayushsomani memory cycle means ,how many clock cycle required to read the memory.since memory speed and cpu speed is different (cpu speed is so high) .

0

Can't we execute all Memory Read/Write in a Single Cycle? Like, We performed three Memory read in OF. 

0
Can someone please explain, how Mem[A] is already given in the instruction itself.

Not able to get this!!!
8 votes
indirect addressing mode will take 2 memory cycles and A[R0] will take 1  memory cycles... Total 4 memory cycles .. Here equation is  A[R0] = A[R0] + @B ...  where A and B are memory addresses ...  A[R0] will be interpreted as A+M[R0] which will produce a memory address ... so 1 memory cycle for it .. So Total 1+1+2 = 4 ...
0

This interpretation is totally incorrect and according to this approach  the answer should be 3..

Check this https://en.wikipedia.org/wiki/Addressing_mode#Indexed_absolute

You'll find that the address of the register where the offset is stored is given, and that doesn't require a memory cycle to fetch....

5 votes
B) as Memory[ A+R0 ]<--Memory[ A+R0 ] + Memory[memory[B]]

edited by
0

 Memory[A] is given as part of the instruction. 

1
Sir ,Which line indicates that Mem[A] is part of inst. i am not able to get this :/
1
@kalpish

thiz one The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes
2 votes

 

ADD A[R0], @B;

 

ANSWER : 6

 

A TOTAL OF 6 MEMORY ADDRESS NEED TO BE ACCESSED TIN ORDER TO PERFORM THE INSTRUCTION.

 

 

THE ABOVE CODE CONTAINS 3 PARTS:

1. DISPLACEMENT ADDRESSING  A[R0] 

2. INDIRECT ADDRESSING @B  

3. ARITHMETIC OPERATION / STORE RESULT ADD

 

 

1. A[R0] RESULTS IN 3 MEMORY ACCESS

EFFECTIVE ADDRESS IS CALCULATED AS

A[R0] = A + (R0)

A[R0] IS  A TYPE OF DISPLACEMENT ADDRESSING MODE IN WHICH THE FINAL MEMORY [A+R0] IS ACCESSED BY ADDING THE BASE ADDRESS "R0" TO THE DISPLACEMENT ADDRESS "A"

  

2. @B FETCHED THE OPERAND IN 2 MEMORY ACCESS SINCE IT IS AN INDIRECT ADDRESSING MODE.

3. ONE MORE MEMORY ACCESS IS REQUIRED IN ORDER TO STORE THE FINAL ADD RESULT IN THE DESTINATION ADDRESS.

 

A TOTAL OF 6 MEMORY ADDRESS NEED TO BE ACCESSED TIN ORDER TO PERFORM THE INSTRUCTION.

  

1
@arjun Sir

Execution Cycle contains - ID( instruction decode), Operand Fetch, Process Data(ALU) +Write Back(if any)

total of 6 cycles are needed to execute this.

Decode Phase - 2 Memory Reference

Operand fetch phase -

    for 2nd Source (@B)  - 2 memory reference to get data

    for 1st Source(A[r0]) - 1 memory reference to get data

Write back phase ( A[r0) <- A(r0) + @B) - 1 memory reference to write data at memory location pointed by (A+r0) address

 

So total of 6 memory reference in execute cycle.

Please explain how 4 Memory references  are needed in this?
0 votes

Correct me, if i am wrong.

0 votes

 

This can also be a solution. Feel free to correct me.

Answer:

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