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+41 votes

Consider a three word machine instruction

$ADD A[R_0], @B$

The first operand (destination) “$A[R_0]$” uses indexed addressing mode with $R_0$ as the index register. The second operand (source) “[email protected]$” uses indirect addressing mode. $A$ and $B$ are memory addresses residing at the second and third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During execution of $ADD$ instruction, the two operands are added and stored in the destination (first operand).

The number of memory cycles needed during the execution cycle of the instruction is:

  1. $3$
  2. $4$
  3. $5$
  4. $6$
asked in CO & Architecture by Veteran (59.5k points)
edited by | 5.2k views

thiz is right answer

consider thiz The number of memory cycles needed during the execution cycle of the instruction is:

nd solve u reach 4 as answer


Refer  Heading -> 3. Two address instructions  in


@Arjun sir @Bikram Sir is everything correct here ?


@junaid ahmad 

is everything correct here ?

No. refer @reena_kandari's comment in selected answer.

@Chhotu Can you mention specifically what's wrong in here .
i dont think something is wrong in his diagram ..

@Arjun sir this link has a mistake actually in 2 and 3 address instructions once we fetch the instruction MAR points to the first word of the instruction and then as we increment MAR by 1 we get the NEXT INSTRUCTIONS ADDRESS we dont get the operands address directly hence we need to fetch those extra two words into temporary registers and then further fetch the operands present in those addresses into the registers 


A link is not working. please update it @junaid ahmad 

@junadahmed the depiction of stages is wrong, as the effective address calculation and ALU operation is performed in the EX stage rather than OF stage, operands are fetched in ID stage itself and the address calculation after the operands are fetched is done through the ALU unit available in the EX stage, see the MULTICYCLE and SINGLE CYCLE implementation of DATA PATH in a CPU.

3 Answers

+64 votes
Best answer

$1$ $\text{memory read}$ to get first operand from memory address A+Ro (A is given as part of instruction)
$1$ $\text{memory read}$ to get address of second operand (since second uses indirect addressing)
$1$ $\text{memory read}$ to get second operand from the address given by the previous memory read
$1$ $\text{memory write}$ to store to first operand (which is the destination)

So, totally 4 memory cycles once the instruction is fetched.

The second and third words of the instruction are loaded as part of the Instruction fetch and not during the execute stage.

answered by Veteran (355k points)
edited by
had it been total cycles needed, we would have to count register references too right? So the answer would have been 6 ?
@Just_bhavana , Register access time is much less than memory access time hence it is not counted..

If it were asked  "no of memory cycles needed for decode and execute phase"..Then in decode phase , we access the second and third word of instruction..So total cycles needed in decode and execute phase = 4 + 2 = 6.
Thanks for the explanation @Habibkhan
but how the remaining 2 words of instruction is fetched

I've updated the image shared by @reena_kandari. Please add this image to the answer to avoid further confusion.


@Chhotu here first the instruction is fetched in fetch phase and the opcode is decoded in the decode phase and then we come where the operands are present after DECODING and then we fetch the operands in OPERAND FETCH PHASE as here this phase is absent we merged it with EXECUTION PHASE hence we need 4 cycles as @Arjun sir specified

I think, This is clearly $CISC$ architecture, So we include write back in execution step. But Had it been $RISC$ then we wouldn't have included write back in execution.

$5$ stages story is primarily of $RISC$ only.
good explanation @habib khan

@arjun sir , 2nd and 3rd word of the instruction only known after decoding the opcode fetched in instruction fetch , then decode fetch must be comes under executuion phase , then 2 extra mr will make 6 memory references, here i m sharing the carl hamachar line in which in fetch cycle only instruction is loaded in instruction register , 

@saket nandan

Yeah,in Carl hamacher it's direct written that fetching operands from memory or processor registers are to be counted under instruction execute phase.

And there are only 2 phases- instruction fetch(which is only fetching instruction from memory) and second is instruction execute, which is everything left to do.


So operand fetch is under instruction execute.

Accordingly, 6 cycles are needed.
+3 votes
B) as Memory[ A+R0 ]<--Memory[ A+R0 ] + Memory[memory[B]]
answered by Loyal (6.8k points)
edited by

 Memory[A] is given as part of the instruction. 

Sir ,Which line indicates that Mem[A] is part of inst. i am not able to get this :/

thiz one The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes
+3 votes
indirect addressing mode will take 2 memory cycles and A[R0] will take 1  memory cycles... Total 4 memory cycles .. Here equation is  A[R0] = A[R0] + @B ...  where A and B are memory addresses ...  A[R0] will be interpreted as A+M[R0] which will produce a memory address ... so 1 memory cycle for it .. So Total 1+1+2 = 4 ...
answered by Boss (10.9k points)

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