I1: R0<= M[loc1]
lets break it down to all stages...
as that given program was executing in a pipelined processor at a certain time PC got this address of the above instruction while executing a previous instruction..say I0
now its turn for I1.
first in IF CYCLE the instruction was fetch from the memory location previously pointed by pc.
now hypothetically imagine :>>
say instruction was 0-101-11-10 (say 8 bit address)
now in RD phase its its decoded like this.:::>>>>
0 means direct address i.e. loc1=10
101 means load operation
11 means register R0
10 is the address of loc1(we still dont know whats the data in loc1)
no register to be read for this instruction as u can see
in EX phase if it was an indirect address or indexed or relative address the effective address would have been computed..
still don't know whats the data in loc1.
now in MA phase actual load happens.
the data from mem location loc1(i.e. 10) on R0
so only after MA phase we got correct value in R0
that's why operand forwarded from MA and not from EX.