7.5k views

Consider the following data path of a CPU.

The ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation – the first one for loading address in the MAR and the next one for loading data from the memory bus into the MDR.

The instruction “add R0, R1” has the register transfer interpretation R0 <= R0 + R1. The minimum number of clock cycles needed for execution cycle of this instruction is:

1. $2$
2. $3$
3. $4$
4. $5$

edited | 7.5k views
+1
In the ques. it is given that one cycle for loading data to MAR and second for read the data from MBR. so firstly we need to fetch the data from memory for which itself requires 4 cycle for both registers bcoz 2 for MAR and MDR for r0 and similarly for r1. so how come the ans. will be 3? plz explain clearly....
+3
@purubgp

No ,it is total 2 clock cycles are needed for memory read operation , 1 clock cycle for MAR ( memory address register ) another clock cycle for MDR ( memory data register ) . But this is part of Instruction cycle , not the execution cycle.

For execution there is 3 cycles only . Question asks minimum number of clock cycles needed for execution cycle .

1 clock cyle for R0 to S

2nd clock cycle for R1 to T

3rd clock cycle for add operation means R0 + R1 .

so for execution only 3 cycles require .
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if anyone comes up with a better explanation then please post it.As all explanations are confusing
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3??
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1 cycle to place R0 into S

1 cycle to place R1 into T

1 cycle R0<-S+T
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won't it be like 2 cycles for reading R0 and 2 cycles for R1 and the 1 cycle for add. It's mentioned two cycles for memory read operation.
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The question ask for minimum number of clock cycles during the execution cycle of this instructions
1 clock cycle for Add operation
1 clock cycle for selecting destination register using MAR
1 clock cycle for storing data in destination register using MDR.

Total 3 clock cycles.
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Gupta731 whats ur question

The minimum number of clock cycles needed for execution of this instruction is

or

The minimum number of CPU clock cycles needed during the execution cycle of this instruction is

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i think first part
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they just confuse us with instruction cycle and execution cucle
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yeah I got it.

instruction fetch require two cycles but question asks how many clock cycles are required for execution part only !

Now for execution:

(1) $R1_{out}, S_{in}\qquad S \leftarrow R0 \quad -1$ $^{st}$ cycle

(2) $R2_{out}, T_{in}\qquad T \leftarrow R1 \quad - 2^{nd}$ cycle

(3) $S_{out}, T_{out}, \text{Add } R0_{in} \quad R0 \leftarrow R0 + R1 \quad - 3^{rd}$ cycle

So, 3 cycles for execution.

As it is asked for only execution cycles no of cycles $=3.$

If it has been asked for instruction cycles then answer will be $5.$

Hence, option B is correct.

by Boss (31.4k points)
edited
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It will take Five instructions cycle mean? I didn't get plz
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@Bikram sir...sir this question will require 0 fetch cycle as no memory reference there is that the reason..?
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@Shubham Shukla 6 , here we are only concerned about the execution cycle which involves fetching the operands into S and T register as shown by the data path and then adding them..

If we talk about entire instruction cycle , then yes we need 5 cycles as in that case we have to instruction fetch cycles also..As we know instruction is stored in memory and memory reference 2 cycles as per the question hence that will be taken into account if we talk about entire instruction execution , from fetching of instruction to writing the sum into register..
+1
thanks habib
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@pooja ma'am

@habib sir

I have a confusion regarding the fetch phase. It will take 2 memory cycles to get instruction in MDR.  But to bring the it in IR another 1 cycle or the load control of IR is switched on while a movement from MAR to MDR?

In fetch phase 2mem cycles or 3??

+1
How can we assume zero clock cycle as ALU is a combinatorial circuit having some propagation delay.

Do you mean that ALU operation and bus transfer takes place in the same cycle?
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Very nice
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Habibkhan, Instruction fetch will be required $3$ cycles here.

1) $MAR<--[PC]$

2)Load the data from external memory bus to $MDR$

3)$IR<--MDR$

first two steps for reading the data from memory  into MDR but we need one more cycle to store the instruction into Instruction register.

+1

why are we here not considering fourth cycle for transferring the result from ALU to R0 ?

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Hi,

I have a question regarding two clock cycles taken by two register transfers one R0 to S and other R1 to T, doesn't this take a single clock cycle during EX phase in the Multicycle Datapath of a MIPS CPU, both of these transfers can be done parellely.

Can someone help me understand, how can we know about these three operations (two register transfer and one ALU operation) to be taking 3 clock cycles rather than one or two, by looking at the datapath itself, I can't understand how does these three operations take 1 clock cycle each out of the blue because EX phase in a RISC cpu takes only 1 clock cycle to execute. Please help. Anyone.
+1
Got the answer for execution cycle. But if they would have asked about instruction cycle then, how many clock cycles did fetch phase will take?

MAR<- PC,  1 cycle

IR<- M[MAR], 1 cycle

PC<-PC+1, 1 cycle as incrementation require ALU.

Please correct me if I am wrong.

@bikram sir

@pooja palod
+1
Sir, Why don't we consider separate cycle for ALU operation and R0<=R1 + R2 result store cycle?
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@ BIKRAM

You took one cycle for R0 + R1 and you said that we have to take zero cycles for ALU operation but addition is an ALU operation it must be performed on ALU if you take zero cycles for ALU, you should not take one cycle for R0 + R1 and instead it should be zero so total cycles for execution cycle should be 2 only not 3

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accessing MAR & MDR requires 2 clock cycle.

but to execute this instruction, we don't even have to touch MAR or MDR. but we've to access the local BUS( which is in CPU, unlike system BUS which is outside CPU).

If it would said that acceessing local bus takes 1 clock cycle, then the above ans will be correct.

as for executing the given instruction we're accessing local bus everytime.
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Instruction fetch $2$ cycles?
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yes.

but qsn asks for instruction execution cycle time

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Any Good resource for reading ALU and Data path? I mean, i am really confused in calculating the No. of CPU Cycles required.

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• What is the difference between clock cycles needed and CPU clock cycles needed?
• Although, answer is correct for no. of clock cycles needed in execution phase of this instruction. But, no. of clock cycles needed for complete instruction should be 6 and not 5. Coz, IF/ID phase requires 3 clock cycles (2 for memory read and 1 for $MDR_{out}, IR_{in}$). Correct me, if i am wrong.
• Can we perform $R_{0 in}, R_{1 in}$ in the same clock cycle?
• Can we do multiple Memory read/write operation in same clock cycle?
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Shouldn't the 3rd cycle be R0<-S+T ?
S <- R0 ...... 1cycle ( Since the buses are of same size as the

T <- R1 ...... 2nd cycle

R0 <- R0 + R1  ..... 3rd cycle

therefore we need 3 cycles.
by Loyal (7.4k points)
0
will operand fetch not be the part of execution ?
+13

If One wonders why S <- R0 is one cycle.

It is given,

Means PC to MAR one cyle, and it is given all registers are same size. so  R0 to S also one cycle.

+4
because its register to register operation which doesnt involve memory read operation. We are assuming that operands are present in R0 and R1 already.

All the answers here are a tad confusing, I want to share my solution with evidences from the book "Computer Organisation and Embedded System" by Hamacher et al

In the book it is clearly mentioned that

Instruction processing consists of two phases: the fetch phase and the execution phase. It is convenient to divide the processor hardware into two corresponding sections. One section fetches instructions and the other executes them.

The section that fetches instructions is also responsible for decoding them and for generating the control signals that cause appropriate actions to take place in the execution section. The execution section reads the data operands specified in an instruction, performs the required computations, and stores the results.

Considering this in mind we can approach this question with each stage in the Execution cycle to be taking 1 clock cycle each, that is :

Execution Cycle : OF + Compute + WB

OF : 1 clock cycle for Sin←R0 and Tin←R1 both (as both can be done parellely)

Compute : 1 clock cycle for ALUout←S+T

WB : 1 clock cycle for writing the result R0in←ALUout

So in total 3 clock cycles are needed for the Execution cycle.

P.S - We don't have to assume anything at our end until and unless it is explicitly stated in the question, and the statement

### The instruction “add R0, R1” has the register transfer interpretation

doesn't mean that only register operations are to be considered for the clock cycle but it is providing the interpretation for the instruction to be R0 <= R0 + R1 and nothing else, please don't misinterpret it.

by (395 points)
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How Sin←R0 and Tin←R1  can run in parallel...when the bus is in control of S then how it can be given to T at the same time.

+1

R0  <= R+R1

The sequence of instruction take place

I Cycle : R1 out  , Sin

II Cycle: Ro out  , Tin

III Cycle: Sout  ,   Tout , ALU , Rin therefore 3 cycle required

by Boss (16.5k points)
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whats the diff btw execution cycle and instruction cycle??
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@akriti sood, Instruction Cycle for fetching of instruction and execution cycle is for execution of instructions. Also, at the same time instructions/operands may be fetched. :). Hope you get it.
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Instruction cyle means

1. Fetch cycle
2. Execution cycle
• PC to MAR
• M[MAR] to MBR,PC+STEPSIZE
• MBR to IR
+1 vote

This question seems to confusing , as , the first instrtuction does not require any memory reference ..
So during the execution cycle , it will take only the clock cycles needed for ADD instruction which is not given

by Active (1.2k points)
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No, see answer by Umang, if u get something ..
+2

For execution there is 3 cycles only require . Question asks minimum number of clock cycles needed for execution cycle .

1 clock cyle for R0 to S

2nd clock cycle for R1 to T

3rd clock cycle for add operation means R0 + R1 .

And nothing saud about ALU operation so we assume no clock cycle needed for ALU operation !!

so for execution only 3 cycles require .

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@bikram sir, but one more thing, isn't addition an ALU operation only? If not then what exactly is an alu operation?
+1
YES it is ALU operation, But since here Number of cycle needed for ALU is not given so we take it as 0.
0

yes, addition is an ALU operation but in this question no cycle is mention about ALU operation.

so we dont consider any cycle for ALU operation as per question here .

Hope you got my point now why 3 clock cycles is needed .

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@Bikram sir, Sir will the result of addition from registers S and T will directly be stored in register R0? Don't we need another clock cycle to transfer this result from accumulator to GPR R0? In that case, this transfer should also be a part of instruction execution cycle?

https://gateoverflow.in/1388/gate2005-65

In the above similar question we are counting writing in the memory as an independent memory cycle in execution phase, then what is the difference between the two questions.

by Junior (817 points)