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+20 votes

Consider the following data path of a CPU.


The ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation – the first one for loading address in the MAR and the next one for loading data from the memory bus into the MDR.

The instruction “add R0, R1” has the register transfer interpretation R0 <= R0 + R1. The minimum number of clock cycles needed for execution cycle of this instruction is:

  1. 2
  2. 3
  3. 4
  4. 5
asked in CO & Architecture by Veteran (69k points)
retagged by | 3.7k views
In the ques. it is given that one cycle for loading data to MAR and second for read the data from MBR. so firstly we need to fetch the data from memory for which itself requires 4 cycle for both registers bcoz 2 for MAR and MDR for r0 and similarly for r1. so how come the ans. will be 3? plz explain clearly....

No ,it is total 2 clock cycles are needed for memory read operation , 1 clock cycle for MAR ( memory address register ) another clock cycle for MDR ( memory data register ) . But this is part of Instruction cycle , not the execution cycle.

For execution there is 3 cycles only . Question asks minimum number of clock cycles needed for execution cycle .

1 clock cyle for R0 to S

2nd clock cycle for R1 to T

3rd clock cycle for add operation means R0 + R1 .

so for execution only 3 cycles require .

4 Answers

+21 votes
Best answer
instruction fetch require two cycles but question asks how many clock cycles require for execution part only !

now for execution

1 ) R1 out,Sin   S <- R0 ...... 1st cycle

2) R2 out,Tin,    T <- R1 ...... 2nd cycle

3)S out Tout Add R0 in  , R0 <- R0 + R1  ..... 3rd cycle

so 3 cycles for execution

as it is asked for only execution cycles no of cycles=3

If it has been asked for instruction cycles then ans will be 5

hence option B is correct.
answered by Veteran (34.3k points)
edited by

Udit Gupta 1  

I am not able to relate to Sout, Rin terms here

this is Sout means S is out from the ALU

Rin means  R goes into the ALU.... simple :)

It will take Five instructions cycle mean? I didn't get plz
@Bikram sir...sir this question will require 0 fetch cycle as no memory reference there is that the reason..?
@Shubham Shukla 6 , here we are only concerned about the execution cycle which involves fetching the operands into S and T register as shown by the data path and then adding them..

If we talk about entire instruction cycle , then yes we need 5 cycles as in that case we have to instruction fetch cycles also..As we know instruction is stored in memory and memory reference 2 cycles as per the question hence that will be taken into account if we talk about entire instruction execution , from fetching of instruction to writing the sum into register..
thanks habib
@pooja ma'am

@habib sir

I have a confusion regarding the fetch phase. It will take 2 memory cycles to get instruction in MDR.  But to bring the it in IR another 1 cycle or the load control of IR is switched on while a movement from MAR to MDR?

In fetch phase 2mem cycles or 3??

Please help :(
How can we assume zero clock cycle as ALU is a combinatorial circuit having some propagation delay.

Do you mean that ALU operation and bus transfer takes place in the same cycle?
Very nice

Habibkhan, Instruction fetch will be required $3$ cycles here.

1) $MAR<--[PC]$ 

2)Load the data from external memory bus to $MDR$


first two steps for reading the data from memory  into MDR but we need one more cycle to store the instruction into Instruction register.

why are we here not considering fourth cycle for transferring the result from ALU to R0 ?

+11 votes
S <- R0 ...... 1cycle ( Since the buses are of same size as the

T <- R1 ...... 2nd cycle

R0 <- R0 + R1  ..... 3rd cycle

therefore we need 3 cycles.
answered by Boss (7.5k points)
will operand fetch not be the part of execution ?

If One wonders why S <- R0 is one cycle. 

It is given,

"Two clock cycles are needed for memory read operation – the first one for loading address in the MAR...."

Means PC to MAR one cyle, and it is given all registers are same size. so  R0 to S also one cycle.

because its register to register operation which doesnt involve memory read operation. We are assuming that operands are present in R0 and R1 already.
+6 votes

R0  <= R+R1

The sequence of instruction take place 

I Cycle : R1 out  , Sin

II Cycle: Ro out  , Tin

III Cycle: Sout  ,   Tout , ALU , Rin therefore 3 cycle required 

answered by Veteran (16k points)
whats the diff btw execution cycle and instruction cycle??
@akriti sood, Instruction Cycle for fetching of instruction and execution cycle is for execution of instructions. Also, at the same time instructions/operands may be fetched. :). Hope you get it.

Instruction cyle means

  1. Fetch cycle
  2. Execution cycle 
  • PC to MAR
  • MBR to IR
+1 vote

This question seems to confusing , as , the first instrtuction does not require any memory reference ..
So during the execution cycle , it will take only the clock cycles needed for ADD instruction which is not given

answered by Junior (681 points)
@bikram sir Is the above answer correct? Please help.
No, see answer by Umang, if u get something ..


shraddha priya 

For execution there is 3 cycles only require . Question asks minimum number of clock cycles needed for execution cycle .

1 clock cyle for R0 to S

2nd clock cycle for R1 to T

3rd clock cycle for add operation means R0 + R1 .

And nothing saud about ALU operation so we assume no clock cycle needed for ALU operation !!

so for execution only 3 cycles require .

@bikram sir, but one more thing, isn't addition an ALU operation only? If not then what exactly is an alu operation?
YES it is ALU operation, But since here Number of cycle needed for ALU is not given so we take it as 0.

shraddha priya

yes, addition is an ALU operation but in this question no cycle is mention about ALU operation.

so we dont consider any cycle for ALU operation as per question here .

Hope you got my point now why 3 clock cycles is needed .


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