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Consider the following data path of a $\text{CPU}.$

The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including incrementation of the $\text{PC}$ and the $\text{GPRs}$ are to be carried out in the $\text{ALU}.$ Two clock cycles are needed for memory read operation – the first one for loading address in the $\text{MAR}$ and the next one for loading data from the memory bus into the $\text{MDR}.$

The instruction $``\text{add R0, R1}”$ has the register transfer interpretation $\text{R0} \Leftarrow \text{R0 + R1}.$ The minimum number of clock cycles needed for execution cycle of this instruction is:

  1. $2$
  2. $3$
  3. $4$
  4. $5$
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6 Answers

Best answer
72 votes
72 votes

Instruction fetch requires two cycles but the question asks for the execution part only!

Now for execution:

  1. $R1_{out}, S_{in}\qquad S \leftarrow R0 \quad -1^{st}$ cycle
  2. $R2_{out}, T_{in}\qquad T \leftarrow R1 \quad - 2^{nd}$ cycle
  3. $S_{out}, T_{out}, \text{Add } R0_{in} \quad R0 \leftarrow R0 + R1  \quad -  3^{rd}$ cycle

So, $3$ cycles for execution.

As it is asked for only execution cycles, no of cycles required $=3.$

Had it been asked for instruction cycles, then the answer will be $5.$

Hence, option B is correct.

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13 votes
13 votes
S <- R0 ...... 1cycle ( Since the buses are of same size as the

T <- R1 ...... 2nd cycle

R0 <- R0 + R1  ..... 3rd cycle

therefore we need 3 cycles.
8 votes
8 votes

All the answers here are a tad confusing, I want to share my solution with evidences from the book "Computer Organisation and Embedded System" by Hamacher et al

In the book it is clearly mentioned that

Instruction processing consists of two phases: the fetch phase and the execution phase. It is convenient to divide the processor hardware into two corresponding sections. One section fetches instructions and the other executes them.

The section that fetches instructions is also responsible for decoding them and for generating the control signals that cause appropriate actions to take place in the execution section. The execution section reads the data operands specified in an instruction, performs the required computations, and stores the results.

Considering this in mind we can approach this question with each stage in the Execution cycle to be taking 1 clock cycle each, that is :

Execution Cycle : OF + Compute + WB

OF : 1 clock cycle for Sin←R0 and Tin←R1 both (as both can be done parellely)

Compute : 1 clock cycle for ALUout←S+T

WB : 1 clock cycle for writing the result R0in←ALUout

So in total 3 clock cycles are needed for the Execution cycle.

P.S - We don't have to assume anything at our end until and unless it is explicitly stated in the question, and the statement 

The instruction “add R0, R1” has the register transfer interpretation

doesn't mean that only register operations are to be considered for the clock cycle but it is providing the interpretation for the instruction to be R0 <= R0 + R1 and nothing else, please don't misinterpret it.

6 votes
6 votes

R0  <= R+R1

The sequence of instruction take place 

I Cycle : R1 out  , Sin

II Cycle: Ro out  , Tin

III Cycle: Sout  ,   Tout , ALU , Rin therefore 3 cycle required 

Answer:

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